AK7755EN_16 Datasheet, PDF (52/109 Pages) Asahi Kasei Microsystems – DSP with Mono ADC Stereo CODEC + Mic/Lineout Amp

[AK7755]
■ Power-up Sequence
1. When not downloading settings and programs from EEPROM
The AK7755 should be powered up when the PDN pin = “L”. AVDD and TVDD must be powered up first
before DVDD when DVDD is supplied externally (LDOE pin = “L”). In this case, the power-up sequence
between AVDD and TVDD is not critical. Control register settings are initialized by the PDN pin = “L”.
Set the PDN pin to “H” to start the power supply circuits for REF (analog reference voltage source)
generator and digital circuits (only when LDOE pin = “H”) after all power supplies are fed. Control register
access must be made after 1ms from the PDN pin = “H”. Set AINE bit (CONT00: D3) to “1” fist when
using the IN1/INP1, IN2/INN1, IN3/INP2 and IN4/INN2 pins as analog inputs.
The PLL starts operation by a clock reset release (CKRESETN bit (CONT01: D0) = “0” → “1”) and
generates the internal master clock after setting control registers. Therefore, necessary system clock must be
input and control register settings for CONT00 ~ CONT01 are must be finished before releasing the clock
reset.
Interfacing with the AK7755 except control register settings should be made when PLL oscillation is
stabilized after clock reset release (take a 10ms interval or confirm “H” level output of PLLLOCK signal
from the STO/RDY pin) (Figure 24). However, DSP program and coefficient data can be written even
when the system clock is stopped. DSP programs and coefficient data can be written in 1ms by setting
DLRDY bit =“0” → “1” (CONT0F, D0). DLRDY bit (CONT0F: D0) must be set to “0” after the download
(Figure 25).
When using a crystal oscillator in master mode, set the CKM[2:0] bits (CONT00: D6-D4) = 0h or 1h, and
release the clock reset after crystal oscillation is stabilized. The stabilizing time of crystal oscillation is
dependent on the crystal and external circuits.
The system clock must not be stopped except during the clock reset and power-down mode.
TVDD,AVDD
DVDD
PDN (pin)
SI(SPI),SDA(I2C)
CKRESETN bit (Reg.)
DSPRESETN bit(Reg.)
CRESETN bit(Reg.)
XTI,BICK (pin)
Internal PLLCLK
(Internal Master Clock)
CONT Reg. Setting
Clock Stabilizataion
DSP Program
Power OFF
600ns(min) 1ms(min)
Before PLL stable oscillation
access is not permitted
(10ms)
Command code and DSP
Program download
（No time limitation）
Figure 24. Power-up Sequence 1 (When not downloading from EEPROM)
(With External Power Supply (LDOE pin = “L”), No downloading from EEPROM)
014006643-E-00
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2014/10