AK7755EN_16 Datasheet, PDF (32/109 Pages) Asahi Kasei Microsystems – DSP with Mono ADC Stereo CODEC + Mic/Lineout Amp

[AK7755]
CONT01: Clock Setting 2 and JX2 Setting
Write during clock reset.
W R Name D7
C1h 41h CONT01 JX2E
D6
LR
DOWN
D5 D4
BITFS BITFS
[1] [0]
D3
CLKS
[2]
D2
CLKS
[1]
D1
CLKS
[0]
D0
Default
CK
RESETN
00h
D7: JX2E External Conditional Jump 2 Enable
0: JX2 is Disabled (default), No. 14-pin output (SDOUT3) when OUT3E bit (CONT0A:D2) = “1”
1: JX2 is Enabled, No. 14-pin Input
D6: LRDOWN LRCK Sampling Frequency Select
0: LRCK Sampling frequency set by DFS[2:0] bits (CONT00: D2-D0). (default)
1: LRCK Half frequency of the setting value by DFS[2:0] bits
The AK7755 can output the LRCK which is half frequency of the setting value by DFS[2:0] bits
in master mode (CKM mode 0, 1(CONT00: D6-D4)). This mode is used when
LRCK/BICK/SDIN1/SDOUT1 is driven by fs= 8kHz while the AK7755 is driven by fs= 16kHz
in master mode. LRDOWN bit = “1” cannot be set when TDM256 bit (CONT02: D7) = “1”.
D5, D4: BITFS[1:0] BICK fs Select
BITFS BITFS
mode [1:0]
BICK Note
0
00
64fs 512kHz(@fs=8kHz),3.072MHz(@fs=48kHz)
(default)
1
01
48fs 384kHz(@fs=8kHz),2.304MHz(@fs=48kHz)
2
10
32fs 256kHz(@fs=8kHz),1.536MHz(@fs=48kHz)
3
11
256fs 2.048MHz(@fs=8kHz),12.288MHz(@fs=48kHz)
This setting is valid in both slave and master modes.
Set the BICK input sampling frequency against LRCK, in Slave mode (CKM2, 3 and 5).
Set the BICK output sampling frequency against LRCK in Master mode (CKM0 and 1).
The BICK output will be in two different frequencies if setting BITFS[1:0] bits = 1h (48kHz) when
the sampling frequency is 12kHz, 24kHz, 48kHz or 96kHz (DFS[2:0]).
D3, D2, D1: CLKS[2:0] CLKO Output Clock Select
CLKS mode CLKS[2:0] fs=48kHz
fs=44.1kHz
0
000
12.288MHz 11.2896MHz
1
001
6.144MHz
5.6448MHz
2
010
3.072MHz
2.8224MHz
3
011
8.192MHz
7.5264MHz
4
100
4.096MHz
3.7632MHz
5
101
2.048MHz
1.8816MHz
6
110
256fs
256fs
7
111
XTI or BICK XTI or BICK
(default)
D0: CKRESETN Clock Reset
0: Clock Reset (default)
1: Clock Reset Release
014006643-E-00
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2014/10