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AK7755EN_16 Datasheet, PDF (75/109 Pages) Asahi Kasei Microsystems – DSP with Mono ADC Stereo CODEC + Mic/Lineout Amp | |||
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[AK7755]
DSPRESETN bit
CSN
SCLK
donâtcare
SI (L/H)
Command Address DATA
donâtcare
(L/H)
Command Address DATA
donâtcare
(L/H)
RDY = âHâ
Figure 54. Writing to RAM at Random Address Locations (SPI)
7-2. RAM Writing Timing during RUN
These operations are to rewrite the Coefficient RAM (CRAM) and Offset REG (OFREG) during
RUN. Data writing is executed in two steps; write preparation and write execution. The written data
can be confirmed by reading the write preparation data.
1. Write Preparation
After inputting the assigned command code (8 bits) to select the number of data from 1 to 16, input the
starting address of write (16 bits all â0â) and the number of data assigned by command code in this
order. In slave mode, a write preparation command is prohibited for â2 LRCKâ cycles (2/fs) after
releasing DSP reset (DSPRESETN bit).
2. Write Preparation Data Confirmation
After write preparation, prepared data for writing can be confirmed. Address and Data are read in this
order by write preparation data confirmation command â24hâ. The data will be â0x000001â when
reading more than write preparation data. Execute write preparation again when the address and data
are disturbed by external noise.
3. Write Execution
Upon completion of this operation, execute a RAM write during RUN by inputting the corresponding
command code and address (16 bits, all â0â) in this order.
Note 49. Execute write preparation, write preparation read and write execution in this order. When
writing to RAM without a write preparation sequence, a malfunction occurs. Access operation
by a microcontroller is prohibited until RDY changes to âHâ.
Write modification of the RAM content is executed whenever the RAM address for modification is
assigned. For example, when 5 data are written, from RAM address â10â, it is executed as shown
below.
RAM execution address
Write execution position
7 8 9 10 11 13 16 11 12 13 14 15
ââ
âââ
âââ
âââ
Note 50. Address â13â is not executed until rewriting address â12â.
014006643-E-00
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2014/10
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