AK5700 Datasheet, PDF (8/61 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono ADC with PLL & MIC-AMP

ASAHI KASEI
[AK5700]
SWITCHING CHARACTERISTICS
(Ta=25°C; AVDD=2.4 ∼ 3.6V; DVDD=1.6 ∼ 3.6V; C_L=20pF; unless otherwise specified)
Parameter
Symbol
min
typ
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
-
Pulse Width Low
tCLKL 0.4/fCLK
-
Pulse Width High
tCLKH 0.4/fCLK
-
MCKO Output Timing
Frequency
fMCK
0.2352
-
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
256fs at fs=32kHz, 29.4kHz
dMCK
-
33
LRCK Output Timing
Frequency
fs
7.35
-
DSP Mode: Pulse Width High
tLRCKH
-
tBCK
Except DSP Mode: Duty Cycle
Duty
-
50
BCLK Output Timing
Period
BCKO1-0 bit = “01”
tBCK
-
1/(32fs)
BCKO1-0 bit = “10”
tBCK
-
1/(64fs)
Duty Cycle
dBCK
-
50
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
-
Pulse Width Low
tCLKL 0.4/fCLK
-
Pulse Width High
tCLKH 0.4/fCLK
-
MCKO Output Timing
Frequency
fMCK
0.2352
-
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
256fs at fs=32kHz, 29.4kHz
dMCK
-
33
EXLRCK Input Timing
Frequency
DSP Mode: Pulse Width High
fs
7.35
-
tLRCKH tBCK−60
-
Except DSP Mode: Duty Cycle
Duty
45
-
EXBCLK Input Timing
Period
tBCK
1/(64fs)
-
Pulse Width Low
tBCKL 0.4 x tBCK
-
Pulse Width High
tBCKH 0.4 x tBCK
-
PLL Slave Mode (PLL Reference Clock = EXLRCK pin)
EXLRCK Input Timing
Frequency
DSP Mode: Pulse Width High
fs
7.35
-
tLRCKH tBCK−60
-
Except DSP Mode: Duty Cycle
Duty
45
-
EXBCLK Input Timing
Period
tBCK
1/(64fs)
-
Pulse Width Low
tBCKL 0.4 x tBCK
-
Pulse Width High
tBCKH 0.4 x tBCK
-
max
Units
27
-
-
12.288
60
-
48
-
-
-
-
-
MHz
ns
ns
MHz
%
%
kHz
ns
%
ns
ns
%
27
MHz
-
ns
-
ns
12.288 MHz
60
%
-
%
48
kHz
1/fs − tBCK ns
55
%
1/(32fs)
ns
-
ns
-
ns
48
kHz
1/fs − tBCK ns
55
%
1/(32fs)
ns
-
ns
-
ns
MS0569-E-01
-8-
2006/12