AK5700 Datasheet, PDF (34/61 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono ADC with PLL & MIC-AMP

ASAHI KASEI
[AK5700]
„ ALC Operation
The ALC (Automatic Level Control) is done by ALC block when ALC bit is “1”.
1. ALC Limiter Operation
During the ALC limiter operation, when the output exceeds the ALC limiter detection level (Table 22), the IVL value is
attenuated automatically by the amount defined by the ALC limiter ATT step (Table 23).
When ZELMN bit = “0” (zero cross detection is enabled), the IVL value is changed by ALC limiter operation at the
individual zero crossing point of zero crossing timeout. ZTM1-0 bits set the zero crossing timeout period of both ALC
limiter and recovery operation (Table 24).
When ZELMN bit = “1” (zero cross detection is disabled), IVL value is immediately (period: 1/fs) changed by ALC
limiter operation. Attenuation step is fixed to 1 step regardless as the setting of LMAT1-0 bits.
The attenuation operation is done continuously until the input signal level becomes ALC limiter detection level (Table 22)
or less. After completing the attenuation operation, unless ALC bit is changed to “0”, the operation repeats when the input
signal level exceeds LMTH1-0 bits.
LMTH1
0
0
1
1
LMTH0 ALC Limier Detection Level ALC Recovery Waiting Counter Reset Level
0
ALC Output ≥ −2.5dBFS
−2.5dBFS > ALC Output ≥ −4.1dBFS
1
ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
0
ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
1
ALC Output ≥ −8.5dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
Table 22. ALC Limiter Detection Level / Recovery Counter Reset Level
Default
ZELMN
0
1
LMAT1 LMAT0
ALC Limiter ATT Step
0
0
1 step
0.375dB
0
1
2 step
0.750dB
1
0
4 step
1.500dB
1
1
8 step
3.000dB
x
x
1step
0.375dB
Table 23. ALC Limiter ATT Step
Default
ZTM1
0
0
1
1
ZTM0
0
1
0
1
Zero Crossing Timeout Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 24. ALC Zero Crossing Timeout Period
Default
MS0569-E-01
- 34 -
2006/12