AK5700 Datasheet, PDF (27/61 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono ADC with PLL & MIC-AMP

ASAHI KASEI
[AK5700]
„ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”, TE3-0 bits = “0101”, TMASTER bit = “1”)
The AK5700 becomes EXT Master Mode by setting as Figure 45. Master clock is input from MCKI pin, the internal PLL
circuit is not operated. The clock required to operate is MCKI (256fs, 512fs or 1024fs). The input frequency of MCKI is
selected by FS1-0 bits (see Table 12).
Mode
0
1
2
3
FS3-2 bits
Don’t care
Don’t care
Don’t care
Don’t care
FS1 bit FS0 bit
MCKI Input
Frequency
Sampling Frequency
Range
0
0
256fs
7.35kHz ∼ 48kHz
0
1
1024fs
7.35kHz ∼ 13kHz
1
0
512fs
7.35kHz ∼ 26kHz
1
1
256fs
7.35kHz ∼ 48kHz
Table 12. MCKI Frequency at EXT Master Mode
Default
MCKI should always be present whenever the ADC is in operation (PMADC bit = “1”). If MCKI is not provided, the
AK5700 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic
internally. If MCKI is not present, the ADC should be in the power-down mode (PMADC bits = “0”).
AK5700
MCKO
MCKI
BCLK
LRCK
SDTO
256fs, 512fs or 1024fs
32fs or 64fs
DSP or μP
MCLK
BCLK
1fs
LRCK
SDTI
Figure 23. EXT Master Mode
BCKO1 bit BCKO0 bit
BCLK Output
Frequency
0
0
N/A
0
1
32fs
Default
1
0
64fs
1
1
N/A
Table 13. BCLK Output Frequency at Master Mode
MS0569-E-01
- 27 -
2006/12