AK5700 Datasheet, PDF (28/61 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono ADC with PLL & MIC-AMP

ASAHI KASEI
[AK5700]
„ Bypass Mode
When THR bit = “1”, M/S bit = “0” and PMADC bit = “0” input clocks and data of EXLRCK, EXBCLK and EXSDTI
pins are bypassed to LRCK, BCLK and SDTO pins, respectively.
When THR bit = “1”, M/S bit = “0” and PMADC bit = “1” input clocks of EXLRCK and EXBCLK pins are bypassed to
LRCK and BCLK pins, and ADC data is output from SDTO pin.
THR bit
0
M/S bit
0
1
0
1
1
PMADC bit
0
1
0
1
0
1
0
1
BCLK/LRCK
SDTO
“L”
“L”
“L”
ADC data
Output
“L”
Output
ADC data
EXBCLK/EXLRCK EXSDTI
EXBCLK/EXLRCK ADC data
N/A
N/A
Output
ADC data
Table 14. Bypass Mode Select
Mode
Power down
Slave mode
Power down
Master mode
Bypass mode
Slave & Bypass
N/A
Master mode
Figure
Default
Figure 24
Figure 25
DSP or μP
BCLK
LRCK
SDTI
DSP or μP
BCLK
LRCK
SDTI
≥ 32fs
1fs
AK5700
BCLK
EXBCLK
LRCK
SDTO
EXLRCK
EXSDTI
≥ 32fs
1fs
≥ 32fs
1fs
Figure 24. Bypass Mode
AK5700
BCLK
LRCK
SDTO
EXBCLK
EXLRCK
AIN
≥ 32fs
1fs
Analog In
Figure 25. Slave & Bypass Mode
DSP or μP
BCLK
LRCK
SDTO
DSP or μP
BCLK
LRCK
MS0569-E-01
- 28 -
2006/12