AK5700 Datasheet, PDF (30/61 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono ADC with PLL & MIC-AMP

ASAHI KASEI
[AK5700]
EXLRCK / LRCK
(M/S=0)
EXLRCK / LRCK
(M/S=1)
15
EXBCLK(32fs)
BCLK(32fs)
0 12
8 14 15 16 17 18 29 30 31
0 12
8 14 15 16 17 18 13 30 31
SDTO(o)
15 14 ⁸ 2 1 0 15 14
2 1 0 15 14 ⁸ 2 1 0 15 14
1/fs
1/fs
15:MSB, 0:LSB
Figure 26. Mode 0 Timing (BCKP = “0”, MSBS = “0”, M/S = “0” or “1”)
2 10
EXLRCK / LRCK
(M/S=0)
EXLRCK / LRCK
(M/S=1)
15
EXBCLK(32fs)
BCLK(32fs)
0 12
8 14 15 16 17 18 29 30 31
0 12
8 14 15 16 17 18 13 30 31
SDTO(o)
15 14 ⁸ 2 1 0 15 14
2 1 0 15 14 ⁸ 2 1 0 15 14
1/fs
1/fs
15:MSB, 0:LSB
Figure 27. Mode 0 Timing (BCKP = “1”, MSBS = “0”, M/S = “0” or “1”)
2 10
EXLRCK / LRCK
(M/S=0)
EXLRCK / LRCK
(M/S=1)
15
EXBCLK(32fs)
BCLK(32fs)
0 12
8 14 15 16 17 18 29 30 31
0 12
8 14 15 16 17 18 13 30 31
SDTO(o)
15 14 ⁸ 2 1 0 15 14
2 1 0 15 14 ⁸ 2 1 0 15 14
1/fs
1/fs
15:MSB, 0:LSB
Figure 28. Mode 0 Timing (BCKP = “0”, MSBS = “1”, M/S = “0” or “1”)
2 10
EXLRCK / LRCK
(M/S=0)
EXLRCK / LRCK
(M/S=1)
15
EXBCLK(32fs)
BCLK(32fs)
0 12
8 14 15 16 17 18 29 30 31
0 12
8 14 15 16 17 18 13 30 31
SDTO(o)
15 14 ⁸ 2 1 0 15 14
2 1 0 15 14 ⁸ 2 1 0 15 14
1/fs
1/fs
15:MSB, 0:LSB
Figure 29. Mode 0 Timing (BCKP = “1”, MSBS = “1”, M/S = “0” or “1”)
2 10
Note : The data from 0 to 15 bits is the same as from 16 to 31 bits at the Figure 26, Figure 27,
Figure 28, Figure 29
MS0569-E-01
- 30 -
2006/12