AK5700 Datasheet, PDF (12/61 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono ADC with PLL & MIC-AMP

ASAHI KASEI
„ Timing Diagram
MCKI
LRCK
BCLK
MCKO
1/fCLK
VIH
VIL
tCLKH
tCLKL
1/fs
tLRCKH
tLRCKL
tBCK
50%DVDD
Duty = tLRCKH x fs x 100
tLRCKL x fs x 100
tBCKH
tBCKL
1/fMCK
50%DVDD
dBCK = tBCKH / tBCK x 100
tBCKL / tBCK x 100
50%DVDD
tMCKL
dMCK = tMCKL x fMCK x 100
Figure 2. Clock Timing (PLL/EXT Master mode)
[AK5700]
LRCK
BCLK
(BCKP = "0")
tLRCKH
tDBF
tBCK
dBCK
50%DVDD
50%DVDD
BCLK
(BCKP = "1")
SDTO
tBSD
MSB
50%DVDD
50%DVDD
Figure 3. Audio Interface Timing (PLL/EXT Master mode & DSP mode: MSBS = “0”)
MS0569-E-01
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2006/12