AK5700 Datasheet, PDF (23/61 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono ADC with PLL & MIC-AMP

ASAHI KASEI
[AK5700]
When PLL reference clock input is EXLRCK or EXBCLK pin, the sampling frequency is selected by FS3 and FS2 bits
(See Table 6).
Mode ^{FS3 bit FS2 bit}
FS1 bit
FS0 bit
Sampling Frequency
Range
0
0
0
Don’t care Don’t care
7.35kHz ≤ fs ≤ 12kHz
1
0
1
Don’t care Don’t care
12kHz < fs ≤ 24kHz
2
1
Don’t care Don’t care Don’t care
24kHz < fs ≤ 48kHz Default
Others
Others
N/A
Table 6. Setting of Sampling Frequency at PMPLL bit = “1” and Reference=EXLRCK/EXBCLK
„ PLL Unlock State
1) PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
In this mode, LRCK and BCLK pins go to “L” and irregular frequency clock is output from MCKO pins at MCKO bit is
“1” before the PLL goes to lock state after PMPLL bit = “0” Æ “1”. If MCKO bit is “0”, MCKO pin goes to “L” (see
Table 7).
In DSP Mode 0, BCLK and LRCK start to output corresponding to Ach data after PLL goes to lock state by setting
PMPLL bit = “0” Æ “1”. When MSBS and BCKP bits are “01” or “10” in DSP Mode 0, BCLK “H” time of the first pulse
becomes shorter by 1/(256fs) than “H” time except for the first pulse.
When sampling frequency is changed, BCLK and LRCK pins do not output irregular frequency clocks but go to “L” by
setting PMPLL bit to “0”.
PLL State
After that PMPLL bit “0” Æ “1”
MCKO pin
MCKO bit = “0” MCKO bit = “1”
“L” Output
Invalid
BCLK pin
“L” Output
PLL Unlock (except above case)
“L” Output
Invalid
Invalid
PLL Lock
“L” Output
See Table 9
See Table 10
Table 7. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
LRCK pin
“L” Output
Invalid
1fs Output
2) PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
In this mode, an invalid clock is output from MCKO pin before the PLL goes to lock state after PMPLL bit = “0” Æ “1”.
After that, the clock selected by Table 9 is output from MCKO pin when PLL is locked. ADC outputs invalid data when
the PLL is unlocked.
PLL State
After that PMPLL bit “0” Æ “1”
MCKO pin
MCKO bit = “0” MCKO bit = “1”
“L” Output
Invalid
PLL Unlock (except above case)
“L” Output
Invalid
PLL Lock
“L” Output
See Table 9
Table 8. Clock Operation at PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
MS0569-E-01
- 23 -
2006/12