AK5700 Datasheet, PDF (42/61 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono ADC with PLL & MIC-AMP

ASAHI KASEI
[AK5700]
Addr
12H
Register Name
Signal Select
Default
D7
D6
0
0
0
0
D5
D4
D3
D2
D1
D0
0
PMMP
0
MDIF1
0
AIN
0
0
0
0
0
0
AIN: ADC Input Source Select
0: AIN1 pin (Default)
1: AIN2 pin
MDIF1: ADC Input Type Select
0: Single-ended input (AIN1/AIN2 pin: Default)
1: Full-differential input (AIN+/AIN− pin)
PMMP: MPWR pin Power Management
0: Power down: Hi-Z (Default)
1: Power up
Addr
13H
Register Name
Mic Gain Control
Default
D7
D6
D5
D4
D3
0
0
0
0
0
0
0
0
0
0
D2
D1
D0
0
MGAIN1 MGAIN0
0
0
1
MGAIN1-0: MIC-Amp Gain Control (See Table 20)
Default: “01”(+15dB)
Addr
14H
Register Name
Audio Format Select
Default
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
MSBS BCKP DIF1 DIF0
0
0
1
0
0
0
1
1
DIF1-0: Audio Interface Format (See Table 15)
Default: “11” (I²S)
BCKP: BCLK/EXBCLK Polarity at DSP Mode (See Table 16)
“0”: SDTO is output by the rising edge (“↑”) of BCLK/EXBCLK. (Default)
“1”: SDTO is output by the falling edge (“↓”) of BCLK/EXBCLK.
MSBS: LRCK/EXLRCK Polarity at DSP Mode (See Table 16)
“0”: The rising edge (“↑”) of LRCK/EXLRCK is half clock of BCLK/EXBCLK before the channel change.
(Default)
“1”: The rising edge (“↑”) of LRCK/EXLRCK is one clock of BCLK/EXBCLK before the channel change.
MS0569-E-01
- 42 -
2006/12