AK5700 Datasheet, PDF (53/61 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono ADC with PLL & MIC-AMP

ASAHI KASEI
5. EXT Master Mode
[AK5700]
Power Supply
PDN pin
PMVCM bit
(Addr:10H, D2)
MCKI pin
(1)
(2) (3)
M/S bit
(Addr:11H, D1)
TE3-0 bits
(Addr:1DH, D7-4)
TMASTER bit
(Addr:1EH, D1)
"1010"
BCLK pin
LRCK pin
Input
Example:
Audio I/F Format: I2S
BCLK frequency at Master Mode: 64fs
Input Master Clock Select: 256fs
Sampling Frequency: 44.1kHz
(1) Power Supply & PDN pin = “L” Æ “H”
"0101"
Output
(2)Addr:11H, Data:26H
Addr:14H, Data:23H
Addr:15H, Data:2FH
Addr:1DH, Data:50H
Addr:1EH, Data:02H
BCLK and LRCK output
(3)Addr:10H, Data:04H
Figure 45. Clock Set Up Sequence (5)
<Example>
(1) After Power Up: PDN pin “L” Æ “H”
“L” time of 150ns or more is needed to reset the AK5700.
(2) DIF1-0, FS1-0, BCKO1-0, M/S, TE3-0 and TMASTER bits should be set during this period as follows.
(2a) M/S bit = “1”, setting of FS3-0 and BCKO1-0 bits.
(2b) Setting of DIF1-0 bits.
(2c) TE3-0 bits = “0101”
(2d) TMASTER bit = “1”: BCLK and LRCK start to output.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
When the clock mode is changed from EXT Master Mode to other modes, the register should be set as above table after
PDN pin = “L” to “H” or TE3-0 bits = “1010”.
MS0569-E-01
- 53 -
2006/12