AK5700 Datasheet, PDF (36/61 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono ADC with PLL & MIC-AMP

ASAHI KASEI
[AK5700]
3. Example of ALC Operation
Table 28 shows the examples of the ALC setting for mic recording.
Register Name
LMTH
ZELMN
ZTM1-0
WTM1-0
REF7-0
IVL7-0
LMAT1-0
RGAIN1-0
ALC
Comment
fs=8kHz
Data
Operation
Limiter detection Level
01
−4.1dBFS
Limiter zero crossing detection
0
Enable
Zero crossing timeout period
00
16ms
Recovery waiting period
*WTM1-0 bits should be the same data 00
16ms
as ZTM1-0 bits
Maximum gain at recovery operation E1H
+30dB
Gain of IVOL
91H
0dB
Limiter ATT step
00
1 step
Recovery GAIN step
00
1 step
ALC enable
1
Enable
Table 28. Example of the ALC setting
fs=44.1kHz
Data
Operation
01
−4.1dBFS
0
Enable
10
11.6ms
10
11.6ms
E1H
+30dB
91H
0dB
00
1 step
00
1 step
1
Enable
The following registers should not be changed during the ALC operation. These bits should be changed after the ALC
operation is finished by ALC bit = “0” or PMADC bit = “0”.
• LMTH, LMAT1-0, WTM1-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN
Manual Mode
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 16ms@8kHz
Limiter and Recovery Step = 1
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
ALC bit = “1”
WR (IVL7-0) ^{* The value of IVOL should be}
the same or smaller than REF’s
WR (ZTM1-0, WTM1-0)
(1) Addr=18H, Data=91H
(2) Addr=1AH, Data=00H
WR (REF7-0)
(3) Addr=1BH, Data=E1H
WR (LMAT1-0, RGAIN1-0, ZELMN, LMTH1-0; ALC= “1”)
(4) Addr=1CH, Data=81H
ALC Operation
Note : WR : Write
Figure 35. Registers set-up sequence at ALC operation
MS0569-E-01
- 36 -
2006/12