AK5700 Datasheet, PDF (57/61 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono ADC with PLL & MIC-AMP

ASAHI KASEI
[AK5700]
„ Stop of Clock
Master clock can be stopped when ADC is not used.
1. PLL Master Mode
PMPLL bit
(Addr:11H, D0)
M/S bit
(Addr:11H, D1)
MCKO bit
(Addr:16H, D2)
External MCKI
Example:
(1)
Audio I/F Format: I2S
BCLK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
Sampling Frequency: 44.1kHz
"H" or "L"
Input
(1) Addr:11H, Data:10H
(2)
(2) Addr:16H, Data:00H
(3)
(3) Stop an external MCKI
Figure 49. Clock Stopping Sequence (1)
<Example>
(1) Power down PLL: PMPLL=M/S bits = “1” → “0”
(2) Stop MCKO clock: MCKO bit = “1” → “0”
(3) Stop an external master clock.
2. PLL Slave Mode (EXLRCK, EXBCLK pin)
PMPLL bit
(Addr:11H, D0)
EXBCLK
EXLRCK
(1)
(2)
Input
(2)
Input
Example
Audio I/F Format : I2S
PLL Reference clock: EXBCLK
BCLK frequency: 64fs
Sampling Frequency: 44.1kHz
(1) Addr:11H, Data:0CH
(2) Stop the external clocks
Figure 50. Clock Stopping Sequence (2)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop the external EXBCLK and EXLRCK clocks
* Clock stop sequence is the same for Slave&Bypass Mode.
MS0569-E-01
- 57 -
2006/12