AK5700 Datasheet, PDF (10/61 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono ADC with PLL & MIC-AMP

ASAHI KASEI
[AK5700]
Parameter
Symbol
min
typ
Max
Units
Audio Interface Timing (DSP Mode)
Master Mode
LRCK “↑” to BCLK “↑” (Note 17)
tDBF 0.5 x tBCK − 40 0.5 x tBCK 0.5 x tBCK + 40 ns
LRCK “↑” to BCLK “↓” (Note 18)
tDBF 0.5 x tBCK − 40 0.5 x tBCK 0.5 x tBCK + 40 ns
BCLK “↑” to SDTO (BCKP bit = “0”)
tBSD
−70
-
70
ns
BCLK “↓” to SDTO (BCKP bit = “1”)
tBSD
−70
-
70
ns
Slave Mode
EXLRCK “↑” to EXBCLK “↑” (Note 17) tLRB
0.4 x tBCK
-
-
ns
EXLRCK “↑” to EXBCLK “↓” (Note 18) tLRB
0.4 x tBCK
-
-
ns
EXBCLK “↑” to EXLRCK “↑” (Note 17) tBLR
0.4 x tBCK
-
-
ns
EXBCLK “↓” to EXLRCK “↑” (Note 18) tBLR
0.4 x tBCK
-
-
ns
EXBCLK “↑” to SDTO (BCKP bit = “0”) tBSD
-
-
80
ns
EXBCLK “↓” to SDTO (BCKP bit = “1”) tBSD
-
-
80
ns
Audio Interface Timing (Left justified & I²S)
Master Mode
BCLK “↓” to LRCK Edge (Note 19)
tMBLR
−40
-
40
ns
LRCK Edge to SDTO (MSB)
(Except I²S mode)
tLRD
−70
-
70
ns
BCLK “↓” to SDTO
tBSD
−70
-
70
ns
Slave Mode
EXLRCK Edge to EXBCLK “↑” (Note 19) tLRB
50
-
-
ns
EXBCLK “↑” to EXLRCK Edge (Note 19) tBLR
50
-
-
ns
EXLRCK Edge to SDTO (MSB)
(Except I²S mode)
tLRD
-
-
80
ns
EXBCLK “↓” to SDTO
tBSD
-
-
80
ns
Note 17. MSBS, BCKP bits = “00” or “11”
Note 18. MSBS, BCKP bits = “01” or “10”
Note 19. EXBCLK rising edge must not occur at the same time as EXLRCK edge.
MS0569-E-01
- 10 -
2006/12