AK5700 Datasheet, PDF (50/61 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono ADC with PLL & MIC-AMP

ASAHI KASEI
[AK5700]
2. PLL Slave Mode (EXLRCK or EXBCLK pin)
Power Supply
PDN pin
PMVCM bit
(Addr:10H, D2)
PMPLL bit
(Addr:11H, D0)
EXLRCK pin
EXBCLK pin
Internal Clock
(1)
(2) (3)
Example:
Audio I/F Format : I2S
PLL Reference clock: EXBCLK
EXBCLK frequency: 64fs
Sampling Frequency: 44.1kHz
4f₍s₁o₎ f_{Power Supply & PDN pin = “L” Æ “H”}
(2) Addr:11H, Data:0CH
Addr:14H, Data:23H
Addr:15H, Data:2FH
Input
(4)
(3) Addr:10H, Data:04H
(5)
Figure 42. Clock Set Up Sequence (2)
(4) Addr:11H, Data:0DH
<Example>
(1)After Power Up: PDN pin “L” Æ “H”
“L” time of 150ns or more is needed to reset the AK5700.
(2)DIF1-0, FS3-0 and PLL3-0 bits should be set during this period.
(3)Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
(4)PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (EXLRCK or EXBCLK pin) is
supplied. PLL lock time is 160ms(max) when EXLRCK is a PLL reference clock. PLL lock time is 2ms(max)
when EXBCLK is a PLL reference clock and the external circuit at VCOC pin is 10k+4.7nF (Table 4).
(5)Normal operation stats after that the PLL is locked.
MS0569-E-01
- 50 -
2006/12