AK5700 Datasheet, PDF (31/61 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono ADC with PLL & MIC-AMP

ASAHI KASEI
[AK5700]
EXLRCK
LRCK
0 1 23
EXBCLK(32fs)
BCLK(32fs)
8 9 10 11 12 13 14 15 0 1 2 3
8 9 10 11 12 13 14 15 0 1
SDTO(o)
15 14 13 8 7 6 5 4 3 2 1 0 15 14 13 8 7 6 5 4 3 2 1 0 15
0 1 23
EXBCLK(64fs)
BCLK(64fs)
14 15 16 17 18
31 0 1 2 3
14 15 16 17 18
SDTO(o)
15 14 13 13 2 1 0
15:MSB, 0:LSB
15 14 13 1 2 1 0
2
1/fs
Figure 30. Mode 2 Timing (MSB justified, M/S = “0” or “1”)
31 0 1
15
EXLRCK
LRCK
0 1 23 4
EXBCLK(32fs)
BCLK(32fs)
9 10 11 12 13 14 15 0 1
23 4
9 10 11 12 13 14 15 0 1
SDTO(o)
0 15 14 13 7 7 6 5 4 3 2 1 0 15 14 13 7 7 6 5 4 3 2 1 0
0 1 23 4
EXBCLK(64fs)
BCLK(64fs)
14 15 16 17 18
SDTO(o)
15 14 13
210
31 0 1 2 3 4 14 15 16 17 18
15 14 13 2 2 1 0
31 0 1
15:MSB, 0:LSB
1/fs
Figure 31. Mode 3 Timing (I²S, M/S = “0” or “1”)
Note : The data from 0 to 15 bits is the same as when LRCK is “H” or “L” at the Figure 30, Figure 31
MS0569-E-01
- 31 -
2006/12