AK5700 Datasheet, PDF (43/61 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono ADC with PLL & MIC-AMP

ASAHI KASEI
[AK5700]
Addr
15H
Register Name
fs Select
Default
D7
D6
D5
D4
D3
D2
D1
D0
HPF1
HPF0 BCKO1 BCKO0 FS3
FS2
FS1
FS0
0
0
0
1
1
1
1
1
FS3-0: Sampling Frequency Select (See Table 5 and Table 6) and MCKI Frequency Select (See Table 11)
Default: “1111” (44.1kHz)
FS3-0 bits select sampling frequency at PLL mode and MCKI frequency at EXT mode.
BCKO1-0: BCLK Output Frequency Select at Master Mode (See Table 10)
Default: “01” (32fs)
HPF1-0: Offset Cancel HPF Cut-off Frequency and ADC Initialization Cycle (See Table 17, Table 30)
Default: “00” (fc=3.4Hz@fs=44.1kHz, Init Cycle=3088/fs)
Addr
16H
Register Name
Clock Output Select
Default
D7
D6
D5
0
0
0
0
0
0
PS1-0: MCKO Output Frequency Select (See Table 9)
Default: “00”(256fs)
MCKO: Master Clock Output Enable
0: Disable: MCKO pin = “L” (Default)
1: Enable: Output frequency is selected by PS1-0 bits.
THR: Bypass Mode (Table 14)
0: OFF (Default)
1: ON
D4
D3
D2
D1
D0
0
THR MCKO PS1
PS0
0
0
0
0
0
Addr Register Name
18H Input Volume Control
Default
D7
IVL7
1
D6
IVL6
0
D5
IVL5
0
D4
IVL4
1
IVL7-0: Input Digital Volume; 0.375dB step, 242 Level (See Table 29)
Default: “91H” (0dB)
D3
IVL3
0
D2
IVL2
0
D1
IVL1
0
D0
IVL0
1
MS0569-E-01
- 43 -
2006/12