AK5700 Datasheet, PDF (39/61 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono ADC with PLL & MIC-AMP

ASAHI KASEI
[AK5700]
„ Serial Control Interface
Internal registers may be written by using the 3-wire µP interface pins (CSN, CCLK and CDTI). CSP pin selects the
polarity of CSN pin and chip address.
1) CSP pin = “L”
The data on this interface consists of a 2-bit Chip address (Fixed to “10”), Read/Write (Fixed to “1”), Register address
(MSB first, 5bits) and Control data (MSB first, 8bits). Each bit is clocked in on the rising edge (“↑”) of CCLK. Address
and data are latched on the 16th CCLK rising edge (“↑”) after CSN falling edge(“↓”). Clock speed of CCLK is 7MHz
(max). The value of internal registers are initialized by PDN pin = “L”.
CSN
CCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
“1” “0” “1”
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (C1 = “1”, C0 = “0”); Fixed to “10”
READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1”
Register Address
Control data
Figure 37. Serial Control I/F Timing (CSP pin = “L”)
2) CSP pin = “H”
The data on this interface consists of a 2-bit Chip address (Fixed to “01”), Read/Write (Fixed to “1”), Register address
(MSB first, 5bits) and Control data (MSB first, 8bits). Each bit is clocked in on the rising edge (“↑”) of CCLK. Address
and data are latched on the 16th CCLK rising edge (“↑”) after CSN rising edge(“↑”). Clock speed of CCLK is 7MHz
(max). The value of internal registers are initialized by PDN pin = “L”.
CSN
CCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CDTI
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
“0” “1” “1”
C1-C0:
R/W:
A4-A0:
D7-D0:
Chip Address (C1 = “0”, C0 = “1”); Fixed to “01”
READ/WRITE (“1”: WRITE, “0”: READ); Fixed to “1”
Register Address
Control data
Figure 38. Serial Control I/F Timing (CSP pin = “H”)
MS0569-E-01
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2006/12