AK5700 Datasheet, PDF (21/61 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono ADC with PLL & MIC-AMP

ASAHI KASEI
[AK5700]
„ System Clock
OPERATION OVERVIEW
There are the following five clock modes to interface with external devices (see Table 1 and Table 2.)
Mode
PMPLL bit
M/S bit PLL3-0 bits
Figure
PLL Master Mode (Note 22)
1
1
See Table 4 Figure 19
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
1
0
See Table 4 Figure 20
PLL Slave Mode 2
(PLL Reference Clock: EXLRCK or EXBCLK pin)
1
0
See Table 4 Figure 21
EXT Slave Mode
0
0
x
Figure 22
EXT Master Mode (Note 23)
0
0
x
Figure 23
Note 22. If M/S bit = “1”, PMPLL bit = “0” and MCKO bit = “1” during the setting of PLL Master Mode, the invalid
clocks are output from MCKO pin when MCKO bit is “1”.
Note 23. In case of EXT Master Mode, the register should be set as Figure 45.
Table 1. Clock Mode Setting (x: Don’t care)
Mode
PLL Master Mode
PLL Slave Mode
(PLL Reference Clock: MCKI pin)
PLL Slave Mode
(PLL Reference Clock: EXLRCK
or EXBCLK pin)
EXT Slave Mode
EXT Master Mode
MCKO bit
0
1
0
1
MCKO pin
“L”
Selected by
PS1-0 bits
“L”
Selected by
PS1-0 bits
MCKI pin
Selected by
PLL3-0 bits
Selected by
PLL3-0 bits
0
“L”
GND
0
“L”
Selected by
FS1-0 bits
0
“L”
Selected by
FS1-0 bits
Table 2. Clock pins state in Clock Mode
BCLK pin,
EXBCLK pin
BCLK pin
(Selected by
BCKO1-0 bits)
LRCK pin,
EXLRCK pin
LRCK pin
(1fs)
EXBCLK pin EXLRCK pin
(≥ 32fs)
(1fs)
EXBCLK pin
(Selected by
PLL3-0 bits)
EXBCLK pin
(≥ 32fs)
BCLK pin
(Selected by
BCKO1-0 bits)
EXLRCK pin
(1fs)
EXLRCK pin
(1fs)
LRCK pin
(1fs)
„ Master Mode/Slave Mode
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK5700 is power-down mode (PDN pin = “L”) and exits reset state, the AK5700 is slave mode. After exiting reset state,
the AK5700 goes to master mode by changing M/S bit = “1”.
M/S bit
0
1
Mode
Used pins
Slave Mode
EXBCLK, EXLRCK
Master Mode
BCLK, LRCK
Table 3. Select Master/Salve Mode
Default
MS0569-E-01
- 21 -
2006/12