AK5700 Datasheet, PDF (40/61 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono ADC with PLL & MIC-AMP

ASAHI KASEI
[AK5700]
„ Register Map
Addr
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
Register Name
Power Management
PLL Control
Signal Select
Mic Gain Control
Audio Format Select
fs Select
Clock Output Select
Reserved
Input Volume Control
Reserved
Timer Select
ALC Mode Control 1
ALC Mode Control 2
Mode Control 1
Mode Control 2
D7
0
0
0
0
0
HPF1
0
0
IVL7
1
0
REF7
ALC
TE3
0
D6
0
0
0
0
0
HPF0
0
0
IVL6
0
0
REF6
ZELMN
TE2
0
D5
0
PLL3
0
0
1
BCKO1
0
0
IVL5
0
0
REF5
LMAT1
TE1
0
D4
0
PLL2
PMMP
0
0
BCKO0
0
0
IVL4
1
0
REF4
LMAT0
TE0
0
D3
0
PLL1
0
0
MSBS
FS3
THR
0
IVL3
0
ZTM1
REF3
RGAIN1
0
0
D2
PMVCM
PLL0
MDIF1
0
BCKP
FS2
MCKO
0
IVL2
0
ZTM0
REF2
RGAIN0
0
0
D1
0
M/S
0
MGAIN1
DIF1
FS1
PS1
0
IVL1
0
WTM1
REF1
LMTH1
0
TMASTER
D0
PMADC
PMPLL
AIN
MGAIN0
DIF0
FS0
PS0
1
IVL0
1
WTM0
REF0
LMTH0
0
0
Note 26. PDN pin = “L” resets the registers to their default values.
Note 27. “0” must be sent to the register written as “0” and “1” must be sent to the register written as “1”. For addresses
except for 10H to 1EH, data must not be written.
MS0569-E-01
- 40 -
2006/12