AK5700 Datasheet, PDF (46/61 Pages) Asahi Kasei Microsystems – 16-Bit ΔΣ Mono ADC with PLL & MIC-AMP

ASAHI KASEI
[AK5700]
SYSTEM DESIGN
Figure 39 and Figure 40 shows the system connection diagram for the AK5700. An evaluation board [AKD5700] is
available which demonstrates the optimum layout, power supply arrangements and measurement results.
μP
DSP
19 MPWR
EXLRCK 12
External MIC
20 TEST
EXSDTI 11
21 AIN2
AK5700VN MCKO 10
≤ 1u
22 AINʖ
Top View
CSP 9
Internal MIC
0.1 x Cp
(Note)
≤ 1u
Rp
Cp
23 AIN1
24 VCOC
SDTO 8
LRCK 7
DSP
Power Supply
2.4 ∼ 3.6V
Power Supply
1.6 ∼ 3.6V
Analog Ground
Digital Ground
Notes:
- AVSS and DVSS of the AK5700 should be distributed separately from the ground of external controllers.
- All digital input pins should not be left floating.
- When the AK5700 is EXT mode (PMPLL bit = “0”), a resistor and capacitor of VCOC pin is not needed.
- When the AK5700 is PLL mode (PMPLL bit = “1”), a resistor and capacitor of VCOC pin is shown in Table 4.
0.1 x Cp in parallel with Cp+Rp improves PLL jitter characteristics.
- Mic input AC coupling capacitor should be 1μF or less to start the recording within 100ms.
Figure 39. Typical Connection Diagram (MIC Input)
MS0569-E-01
- 46 -
2006/12