HMC703LP4E Datasheet, PDF (49/58 Pages) Hittite Microwave Corporation – 8 GHZ FRACTIONAL SYNTHESIZER

v02.0813
HMC703LP4E
8 GHz fractional synthesizer
Table 22. Reg 09h Charge Pump Register
BIT
TYPE
NAME
W
DEFLT
[6:0]
R/W
CPIdn
7
100
[13:7]
R/W
CPIup
7
100
[20:14] R/W
CPOffset
7
0
[21]
R/W
CPSrcEn
1
0
[22]
R/W
CPSnkEn
1
1
[23]
R/W
CPHiK
1
0
DESCRIPTION
Main Sink Current (20uA steps)
Main Source Current (20uA steps)
Offset current (5uA steps) - See "Charge-Pump Phase offset" for
more information.
Offset current polarity (Source Offset current)
Recommended 0 in integer mode , PFDInv in FRAC modes.
Offset current polarity (Sink Offset current)
Recommended 0 in integer mode ,NOT PFDInv in FRAC modes.
Hi Gain Mode (~4mA CP I boost depending on Vcp) - Use only
with active loop filter configurations, where Vcp is controlled to
offer better phase-noise.
Table 23. Reg 0Ah Modulation Step Register
BIT
TYPE
NAME
W DEFLT
[23:0]
R/W
MODSTEP
24
0
DESCRIPTION
Fractional Modulation Step size for Ramp/Phase Modulation modes
(Ignored in Integer, Normal Fractional, FM, or Exact Freq modes)
This value is signed two’s complement. Positive values ramps up,
negative values ramp down.
Table 24. Reg 0Bh PD Register
BIT
TYPE
NAME
[2:0]
R/W
PFDDly
[3]
R/W
PFDShort
[4]
R/W
PFDInv
[5]
[6]
[7]
[8]
[9]
[12:10]
[14:13]
[16:15]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PFDUpEn
PFDDnEN
PFDForceUp
PFDForceDn
PFDForceMid
PSBiasSel
OpAmpBiasSel
McntClkGateSel
[17]
R/W
[18]
R/W
VDIVExt
LKDProcTesttoCP
W DEFLT
DESCRIPTION
3
1
Dead-zone avoidance delay (0~1 ns, 3~3 ns. > 3 is unused)
1
0
Tie both PD inputs to Ref or Div based on phase select.
1
0
Swap PD inputs for use in inverting loop configurations.
0- Use with a positive tuning slope VCO and passive loop filter
(default)
1- Use with a negative tuning slope, or with an inverting active loop
filter with a positive tuning slope VCO
1
1
0 will disable up pulses from propagating to the CP
1
1
0 will disable dn pulses from propagating to the CP
1
0
1 will force to the top rail.
1
0
1 will force to the bottom rail.
1
0
1 will force to mid-rail
3
0
PS Bias Current
2
3
OpAmp Bias Current
2
3
If the quantized divide ratio is guaranteed to be within a certain
range, this feature can be enabled to reduce toggle activity and
power consumption slightly. (0: 16 to 31, 1: 16 to 127, 2: 16 to 1023,
3: 16 to max)
1
0
Extend VCO Divider Output Pulse width
1
0
Muxes the lock-detect oscillator to the CP force up/dn for observa-
tion.
6 - 49
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