HMC703LP4E Datasheet, PDF (36/58 Pages) Hittite Microwave Corporation – 8 GHZ FRACTIONAL SYNTHESIZER

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HMC703LP4E
8 GHz fractional synthesizer
Figure 39. Charge Pump Gain and Offset Control - Reg09h
Seed Register and AutoSeed Mode
The start phase of the fractional modulator digital phase accumulator (DPA) may be set to any values via the
seed register Reg 05h. If autoseed Reg 06h[8] is set, then the PLL will automatically reload the start phase from
Reg 05h[23:0] into the DPA every time a new fractional fre­quency is selected. If autoseed is not set, then the PLL will
start new fractional frequencies with the value left in the DPA from the last frequency. Hence the start phase will
effectively be random. Certain zero or binary seed values may cause spurious energy correlation at specific
frequencies. Correlated spurs are advantageous only in very special cases where the spurious are known to be far out
of band and are removed in the loop filter. For most cases a pseudo-random seed setting is recom­mended. Further,
since the autoseed always starts the accumulators at the same place, performance is repeatable if autoseed is used.
Reg 05h’s default value typically provides good performance.
Power on Reset
The HMC703LP4E features a hardware Power on Reset (POR) on the digital supply DVDD. All chip reg­isters will be
reset to default states approximately 250 µs after power up of DVDD. Once the supply is fully up, if the power supply
then drops below 0.5 V the digital portion will reset. Note that the SPI control inputs must also be 0 at power-down,
otherwise they will inadvertently power the chip via the ESD protection network.
Power Down Mode
Hardware Power Down
Chip enable may be controlled from the hardware CEN pin 23, or it may be controlled from the serial port. Reg 01h[0] =1
assigns control to the CEN pin. Reg 01h[0] =0 assigns control to the serial port Reg 01h[1]. For hardware test reasons or
some special applications it is possible to force certain blocks to remain on inside the chip , even if the chip is disabled.
See the register Reg 01h description for more details.
Chip Identification
Version information may be read from the synthesizer by reading the content of chip_ID in Reg 00h.
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