HMC703LP4E Datasheet, PDF (29/58 Pages) Hittite Microwave Corporation – 8 GHZ FRACTIONAL SYNTHESIZER

v02.0813
HMC703LP4E
8 GHz fractional synthesizer
Program Reg 03h = 60, Reg 04h = 0
2. Calculate how many reference cycles will occur in 2 ms. Given that Tref = 1 / f_PD = 20ns,

Nbr of Steps = Tramp/Tref = 2ms/20ns = 100,000
3. Calculate the desired N step size, given Start N, Stop N and Nbr of Steps

N_Step_Size_desired = (62.1 - 60.0) / 100,000 = 21u [fractions of N]
4. Quantize the fractional N step into the 24 bit step size
Program Reg 0Ah = 21u x 2²⁴ = round(352.32) = 352
5. Readjust the stop frequency slightly to ensure it falls exactly on a step boundary
Due to step quantization,there will be some finite error in either the sweep time or sweep span.
We have 3 choices:

a) Target an accurate sweep time, sacrifice resolution on stop frequency

Sweep time = 100k cycles = 2 ms

Stop N = Start N + 100,000 x 352/2²⁴ (Keep 100k cycles)
_{Stop N = 60.000 + 35,200,000 / 2}24 ≈ _62.09808
Program Reg 0Ch= 62, Reg 0Dh = 35,200,000 MOD 2²⁴ = 1,645,568 ≈ 0.09808
f_f ≈ 3104.904 (96 kHz lower stop frequency then desired)

b) Target an accurate stop frequency, at the expense of sweep time accuracy

Given step size of 352/2²⁴, how many cycles to get from 60.0 to 62.1

Nbr of Steps = (62.1 - 60.0) / (352/2²⁴) = 100,091.345

Must round to 100,091 steps.

Sweep time = Tref * 100,091 = 2.00182ms (1.82 us longer than desired)

Stop N = 60.0 + 100,091 x 352/2²⁴ ≈ 62.0999927
Program Reg 0Ch= 62, Reg 0Dh = 35,232,032 MOD 2²⁴ = 1,677,600 ≈ 0.0999927
f_f = 3104.99964 MHz (362 Hz lower stop frequency then desired)

c) A combination of situation a and b
6. Program SD_Mode based on desired trigger and ramp/hop profile (Reg 06h[7:5] = 5,6, or 7)
7. Trigger via either the external pin or SPI TRIG bit.

Continue to issue triggers to advance the ramp profile to the next stage...
Sweeper Configuration for Ultra Fine Step Sizes
In cases where finer step size resolution is desired, it is possible to reduce the f_PD, along with performance implications
it has, or use a single-step mode (Reg 06h[23] = 1) and provide a lower frequency clock on the external trigger pin
to reduce the update rate. The HMC703LP4E can generate a lower frequency clock by programming the R divider
appropriately, and not using it for the PD (Reg 06h[21] = 1), but rather routing it out of the HMC703LP4E via the GPO.
The R divider output can then be looped back to the TRIG pin of the HMC703LP4E to use as a low rate trigger. See
“Ref Path ’R’ Divider” for more details.
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