HMC703LP4E Datasheet, PDF (3/58 Pages) Hittite Microwave Corporation – 8 GHZ FRACTIONAL SYNTHESIZER

v02.0813
HMC703LP4E
8 GHz fractional synthesizer
6-3
Table 34. Electrical Specifications (Continued)
Parameter
PHASE NOISE [14]
Flicker Figure of Merit (FOM)[2]
Floor Figure of Merit [11]
Flicker Noise at f_offset
Phase Noise Floor at f_vco with f_pd
VCO referred Phase Noise Contribution
of the PLL vs f_offset, f_vco, f_pd
Jitter
SPURIOUS
Integer Boundary Spurs @~8GHz
LOGIC INPUTS
Switching Theshold (Vsw)
LOGIC OUTPUT
VOH Output High Voltage
VOL Output Low Voltage
Output impedance : Pull Up
Output impedance : Pull Dn
Conditions
Min.
Integer HiK Mode
Integer Normal Mode
Fractional HiK Mode [3]
Fractional Normal Mode [3]
-236
-232
-232
-228
PN_flick = Flicker FOM +20log(f_vco) -10log(f_offset)
PN_floor = Floor FOM + 10log(f_pd) +20log(f_vco/f_pd)
PN = 10log(10(PNflick ^/10) + 10(PNfloor ^/10) )
SSB 100Hz to 100MHz with
HMC508LP5E VCO
[4][5]
offsets less than loop band-
width, f_pd = 50MHz
VIH/VIL within 50 mV of Vsw
38
VDDIO=3.3 V
115
VDDIO=3.3 V
130
Typ.
-270
-233
-230
-230
-227
50
-60
47
VDDIO
0
150
135
DC load
Digital Output Driver Delay
SCK to Digital Output Delay
1.7nsec with a 3 pF load
0.5ns+0.2ns/pF
8.2ns+0.2ns/pF
RF Divider Range
>4GHz Integer Mode
< 4GHz Integer Mode
> 4GHz Fractional Mode
< 4GHz Fractional Mode
16 bit , Even values only
32
16 bit , All values
16
16 bit
40.0
16 bit
20.0
Max.
-231
-228
-227
-225
-52
54
180
210
1.5
131,070
65,535
131,065.0
65,531.0
Units
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
fs
dBc
% VDDIO
V
V
Ohm
Ohm
mA
ns
ns
[1] Frequency is guaranteed across process, voltage and temperature from -40⁰C to 85⁰C.
[2] With high charge-pump current, +12dBm 100MHz sine reference
[3] Fractional FOM degrades about 3dB/octave for prescaler input frequencies below 2GHz
[4] Using 50MHz reference with VCO tuned to within one loop bandwidth of an integer multiple of the PD frequency. Larger
offsets produce better results. See the “Spurious Performance” section for more information.
[5] Measured with the HMC703LP4E evaluation board. Board design and isolation will affect performance.
[6] Internal divide-by-2 should be enabled for frequencies >4GHz
[7] At low RF Frequency, Rise and fall times should be less than 1ns to maintain performance
[8] Slew rate of greater or equal to 0.5 V/ns
[9] Current consumption depends upon operating mode and frequency of the VCO. Typical values are for fractional mode.
[10] Reference input disconnected
[11] Min/Max versus temperature and supply, under typical reference & RF frequencies and power levels
[12] Slew > 0.5V/ns is recommended , see Table 7, Figure 5, Figure 6 for more information.
[13] Operable with reduced spectral performance outside of this range.
[14] This section specifies the Phase Noise contribution of the PLL, solution phase noise with a given VCO, loop filter and
reference requires a closed loop calculation using Hittite PLL Design Tool.
[15] As measured on HMC703LP4E Evaluation board, with 100Ohm external termination.
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