HMC703LP4E Datasheet, PDF (41/58 Pages) Hittite Microwave Corporation – 8 GHZ FRACTIONAL SYNTHESIZER

v02.0813
HMC703LP4E
8 GHz fractional synthesizer
HMC Mode - Serial Port READ Operation
A typical HMC Mode READ cycle is shown in Figure 42.
a. The Master (host) asserts both SEN (Serial Port Enable) and SDI to indicate a READ cycle, followed
by a rising edge SCK. Note: The Lock Detect (LD) function is usually mul­tiplexed onto the LD_SDO
pin. It is suggested that LD only be considered valid when SEN is low. In fact LD will not toggle until
the first active data bit toggles on LD_SDO, and will be restored immediately after the trailing edge
of the LSB of serial data out as shown in Figure 42.
b. The slave (synthesizer) reads SDI on the 1st rising edge of SCK after SEN. SDI high ini­tiates the
READ cycle (RD)
c. Host places the six address bits on the next six falling edges of SCK, MSB first.
d. Slave registers the address bits on the next six rising edges of SCK (2-7).
e. Slave switches from Lock Detect and places the requested 24 data bits on SD_LDO on the next 24
rising edges of SCK (8-31), MSB first .
f. Host registers the data bits on the next 24 falling edges of SCK (8-31).
g. Slave restores Lock Detect on the 32nd rising edge of SCK.
h. SEN is cleared after a minimum delay of t₆. This completes the cycle.
Table 10. SPI HMC Mode - Read Timing Characteristics
Parameter
Conditions
Min.
t1
SEN to SCK setup time
8
t2
SDI setup to SCK time
3
t3
SCK to SDI hold time
3
t4
SEN low duration
20
t5
SCK to SDO delay
t6
SCK to SEN fall
10
Typ.
Max.
8.2ns+0.2ns/pF
Units
ns
ns
ns
ns
ns
ns
Figure 42. HMC Mode Serial Port Timing Diagram - READ
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