HMC703LP4E Datasheet, PDF (30/58 Pages) Hittite Microwave Corporation – 8 GHZ FRACTIONAL SYNTHESIZER

v02.0813
Reference Input Stage
HMC703LP4E
8 GHz fractional synthesizer
Figure 35. Reference Path Input Stage
The reference buffer provides the path from an external reference source (generally crystal based) to the R divider, and
eventually to the phase detector. The buffer has two modes of operation. High Gain (recommended below 200 MHz),
and High frequency, for 200 to 350 MHz operation. The buffer is internally DC biased, with 100 Ω internal termination.
For 50 Ω match, an external 100 Ω resistance to AC ground should be added, followed by an AC coupling capacitance
(impedance < 1 Ohm), then to the XREFP pin of the part.
At low frequencies, a relatively square reference is recommended to keep the input slew rate high. At higher frequencies,
a square or sinusoid can be used. The following table shows the recommended operating regions for different reference
frequencies. If operating outside these regions the part will normally still operate, but with degraded performance.
Minimum pulse width at the reference buffer input is 2.5 ns. For best spur performance when R = 1, the pulse width
should be > (2.5 ns + 8 Tps), where Tps is the period of the VCO at the prescaler input. When R > 1 minimum pulse
width is 2.5 ns.
Table 7. Reference Sensitivity Table
Square Input
Sinusoidal Input
Frequency
Slew > 0.5V/ns
Recommended Swing (Vpp)
(MHz)
Recommended
Min
Max
Recommended
< 10
YES
0.6
2.5
x
10
YES
0.6
2.5
x
25
YES
0.6
2.5
ok
50
YES
0.6
2.5
YES
100
YES
0.6
2.5
YES
150
ok
0.9
2.5
YES
200
ok
1.2
2.5
YES
200 to 350
x
x
x
YES1
Note: For greater than 200 MHz operation, use buffer in High Frequency Mode. Reg 08h[18] = 1
Recommended Power Range (dBm)
Min
Max
x
x
x
x
8
15
6
15
5
15
4
12
3
8
5
10
Input referred phase noise of the PLL when operating at 50 MHz is between -150 and -156 dBc/Hz at 10 kHz offset
depending upon the mode of operation. The input reference signal should be 10dB better than this floor to avoid deg­
radation of the PLL noise contribution. It should be noted that such low levels are only necessary if the PLL is the
dominant noise contributor and these levels are required for the system goals.
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