HMC703LP4E Datasheet, PDF (15/58 Pages) Hittite Microwave Corporation – 8 GHZ FRACTIONAL SYNTHESIZER

v02.0813
HMC703LP4E
8 GHz fractional synthesizer
High Performance Low Spurious Operation
The HMC703LP4E has been designed for the best phase noise and low spurious content possible in an integrated
synthesizer. Spurious signals in a synthesizer can occur in any mode of operation and can come from a number of
sources.
Figure of Merit, Noise Floor, and Flicker Noise Models
The phase noise of an ideal phase locked oscillator is dependent upon a number of factors:
a. Frequency of the VCO, and the Phase detector
b. VCO Sensitivity, kvco, VCO and Reference Oscillator phase noise profiles
c. Charge Pump current, Loop Filter and Loop Bandwidth
d. Mode of Operation: Integer, Fractional modulator style
The contributions of the PLL to the output phase noise can be characterized in terms of a Figure of Merit (FOM) for both
the PLL noise floor and the PLL flicker (1/f) noise regions, as follows:
where:
Ф
2
p
f_o
f_pd
f_m
F_po
F_p1
Phase Noise Contribution of the PLL (rads²/Hz)
Frequency of the VCO (Hz)
Frequency of the Phase Detector (Hz)
Frequency offset from the carrier (Hz)
Figure of Merit (FOM) for the phase noise floor
Figure of Merit (FOM) for the flicker noise region
PLL Phase Noise
Contribution
( ) ^�
2
p
f₀, f_m, f_pd
= ^Fp1f02 + ^{Fp0 f02}
f_m
f_pd
(EQ 1)
6 - 15
Figure 27. Figure of Merit Noise Models for the PLL
If the free running phase noise of the VCO is known, it may also be represented by a figure of merit for both 1/f² , F_v2,
and the 1/f³, F_v3, regions.
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