HMC703LP4E Datasheet, PDF (20/58 Pages) Hittite Microwave Corporation – 8 GHZ FRACTIONAL SYNTHESIZER

v02.0813
HMC703LP4E
8 GHz fractional synthesizer
Table 6. Operational Modes
PLL Operating Mode (SD_MODE = Reg 06h[7:5])
Register
Number
Register Name
0
Fractional
Mode
1
Integer Mode
2
Exact
Frequency
Mode
3
FM (Frequency
Modulation)
Mode
4
PM (Phase
Modulation)
Mode
Function of
Reg 03h
N Integer Part
Nint
N
Nint
Freq 1: Nint
Nint
Function of
Reg 04h
N Fractional
Part
Nfrac
Nfrac
Freq 1: Nfrac
Nfrac
Function of
Reg 0Ah
Aux Register
Phase Step
Function of
Reg 0Ch
Alternate
Integer
Freq 2: Nint
Function of
Reg 0Dh
Alternate
Fractional
Channels / PD
frequency
Freq 2: Nfrac
Additional Functionality
Double Buffer
YES
NO
YES
YES
YES
On Trigger
Updates
frequency,
optionally
initiates phase
Updates
frequency,
optionally
initiates phase
Toggles
frequency (level
sensitive)
Increments /
decrements
phase
Those registers which are unused in a particular mode can take on any value, and are ignored.
5 to 7
Ramp Mode
Start Nint
Start Nfrac
Frequency step
/ reference clock
STOP Nint
STOP Nfrac
YES
Proceeds to
next stage of
ramp
Triggering
Depending on the operating mode, a trigger event is used to change frequency, FM modulate the frequency, modulate
the phase, or advance the frequency ramp profile to its next state. In general the HMC703LP4E can be triggered via
one of three methods. Not all modes support all trigger methods.
1. An external hardware trigger pin-6 (TRIG)
2. SPI write to TRIG BIT in Reg 0Eh[0]
3. SPI write to fractional register Reg 04h (frequency hopping triggers only).
Depending on the mode, the part is sensitive to either the rising edge, or the level of the trigger. The SPI’s TRIG bit
emulates the external TRIG pin, and so it must typically be written to 1 for a trigger, and then back to 0 in preparation
for another trigger cycle. To use the external TRIG pin, it must be enabled via EXTTRIG_EN (Reg 06h[9]).
Fractional Mode or Exact Frequency Mode Frequency Updates
In non-modulated fractional modes (Reg 06h[7:5] = 0 or 2), if the external trigger is enabled, writes to N_INT and N_frac
(Reg 03h and Reg 04h) are internally buffered and wait for an explicit trigger via either the TRIG pin or the SPI’s TRIG
bit before taking effect. If EXTTRIG_EN = 0, the write to N_INT is double-buffered, and waits for a fractional write to
Reg 04h so that both N_INT and N_frac are internally recognized together. See the “Fractional Mode” section for more
information on calculating the fractional multiplier for your application.
Initial Phase Control
On the HMC703LP4E, the user has control of the initial phase of the VCO via the 24-bit SEED Reg 05h. This seed
phase is loaded on the 1st clock cycle following a trigger event, provided that autoseed (Reg 06h [8] = 1) is enabled.
The value in Reg 05h represents the phase of the VCO. For example, if two synthesizers are triggered in parallel, but
one has a SEED of 0.2 (0.2x2²⁴) and the other has a SEED of 0.7 (0.7x2²⁴), the steady state outputs of the two VCOs
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