HMC703LP4E Datasheet, PDF (32/58 Pages) Hittite Microwave Corporation – 8 GHZ FRACTIONAL SYNTHESIZER

v02.0813
HMC703LP4E
8 GHz fractional synthesizer
Figure 37. RF Input Stage- shown with single ended device
RF Path ’N’ Divider
The main RF path ’N’ divider is capable of divide ratios anywhere between 2¹⁶-1 (524,287) and 16 . This divider for
example could divide a 4 GHz input to a PD frequency anywhere between its maximum output limit of 115 MHz to as low
as 7.6 kHz. The ’N’ divider output may be viewed in test mode on LD_SDO by set­ting Reg 0Fh[4:0] = 10d. When
operating in fractional mode the N divider can change by up to +/-4 from the average value. Hence the selected divide
ratio in fractional mode is restricted to values between 2¹⁶-5 (65,531) and 20.
If the VCO input is above 4 GHz then the 8 GHz fixed RF divide-by-2 should be used, Reg 08h[17] = 1. In this case the
integer division range is restricted to even numbers over the range 2*(2¹⁶-5) (131,062) down to 40.
PLL Jitter
The standard deviation of the arrival time of the VCO signal, or the jitter, may be estimated with a simple approximation
if we assume that the locked VCO has a constant phase noise, � ² (f₀ ), at offsets less than the loop 3dB bandwidth and
a 20dB per decade roll off at greater offsets. The simple locked VCO phase noise approximation is shown on the left of
Figure 38.
Figure 38. PLL Phase Noise and Jitter
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