HMC703LP4E Datasheet, PDF (16/58 Pages) Hittite Microwave Corporation – 8 GHZ FRACTIONAL SYNTHESIZER

v02.0813
HMC703LP4E
8 GHz fractional synthesizer
VCO Phase Noise
Contribution
( ) �
2
n
f₀, f_m
=
F_{n 2}f₀₂
f_m²
+
F_n3 f₀₂
f_m³
(EQ 2)
The Figures of Merit are essentially normalized noise parameters for both the PLL and VCO that can allow quick esti-
mates of the performance levels of the PLL at the required VCO, offset and phase detector fre­quency. Normally, the PLL
IC noise dominates inside the closed loop bandwidth of the synthesizer, and the VCO dominates outside the loop band-
width at offsets far from the carrier. Hence a quick estimate of the closed loop performance of the PLL can be made by
setting the loop bandwidth equal to the frequency where the PLL and free running phase noise are equal.
The Figure of Merit is also useful in estimating the noise parameters to be entered into a closed loop design tool such as
Hittite PLL Design, which can give a much more accurate estimate of the closed loop phase noise and PLL loop filter
component values.
Given an optimum loop design, the approximate closed loop performance is simply given by the minimum of the PLL
and VCO noise contributions.
PLL-VCO Noise
( ) ^{� 2}
= min
�
2
p
,
�
2
n
(EQ 3)
An example of the use of the FOM values to make a quick estimate of PLL performance: Estimate the phase noise of an
8 GHz closed loop PLL with a 100 MHz reference operating in Fractional Mode B with the VCO operating at 8 GHz and
the VCO divide by 2 port driving the PLL at 4 GHz. Assume an HMC509 VCO has free running phase noise in the 1/f²
region at 1 MHz offset of -135 dBc/Hz and phase noise in the 1/f³ region at 1 kHz offset of -60 dBc/Hz.
F_{v1_dB} =
-135
Free Running VCO PN at 1MHz offset
+20*log10(1e6)
PNoise normalized to 1Hz offset
-20*log10(8e9)
Pnoise normalized to 1Hz carrier
= -213.1 dBc/Hz at 1Hz
VCO FOM
F_{v3_dB} =
-60
Free Running VCO PN at 1kHz offset
+30*log10(1e3)
PNoise normalized to 1Hz offset
-20*log10(8e9)
Pnoise normalized to 1Hz carrier
= -168 dBc/Hz at 1Hz
VCO Flicker FOM
We can see from Figure 3 and Figure 4 respectively that the PLL FOM floor and FOM flicker parameters in fractional
Mode A:
Fpo_dB = -227 dBc/Hz at 1Hz
Fp1_dB = -266 dBc/Hz at 1Hz
Each of the Figure of Merit equations result in straight lines on a log-frequency plot. We can see in the example below
the resulting
PLL floor at 8 GHz = F_{po_dB} +20log10(fvco) -10log10(fpd) = -227+198 -80 = -109 dBc/Hz
PLL Flicker at 1 kHz = F_{p1_dB}+20log10(fvco)-10log10(fm) = -266 +198-30 = -98 dBc/Hz
VCO at 1 MHz = F_{v1_dB}+20log10(fvco)-20log10(fm)= -213 +198-120
= -135 dBc/Hz
VCO flicker at 1 kHz = F_{v3_dB}+20log10(fvco)-30log10(fm)= -168 +198-90 = -60 dBc/Hz
These four values help to visualize the main contributors to phase noise in the closed loop PLL. Each falls on a linear
line on the log-frequency phase noise plot shown in Figure 27.
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