HMC703LP4E Datasheet, PDF (34/58 Pages) Hittite Microwave Corporation – 8 GHZ FRACTIONAL SYNTHESIZER

v02.0813
HMC703LP4E
8 GHz fractional synthesizer
PD Force Mid Reg 0Bh[9] will disable the charge pump current sources and place a voltage source on the loop filter at
approximately VPPCP/2. If a passive filter is used this will set the VCO to the mid-voltage tun­ing point which can be
useful for testing of the VCO.
Lock Detect
Each PD (Phase Detector) cycle, the HMC703LP4E measures phase error at the PD. The measured phase error must
be:
• < ~220 degrees if 40 MHz <= f_PD <= 120 MHz, and
• < ~14 ns if f_pd < 40 MHz,
for a number of consecutive cycles (number of cycles is programmable in Reg 07h[2:0]), in order for HMC703LP4E to
declare a lock. A single phase error outside of these criteria disqualifies lock, and the lock counter (maximum value of
lock counter = Reg 07h[2:0]) is restarted.
Note that in some cases, the PLL may be locked with a phase error that exceeds 180 degrees, or 12 ns, whichever is
smaller. This can occur if the offset current is inappropriately programmed too high. It is not recommended to operate
in this condition because it leads to degraded phase noise performance. In such a case the lock detect circuit would
not declare a locked condition, even though the PLL is locked.
The HMC703LP4E lock-detect functionality is self-calibrating relative to the reference frequency. Typically the
lock-detect training is only required once on power-up, or each time the reference frequency or the R divider value
(Reg 02h) is changed.
To train the lock-detect circuitry of the HMC703LP4E on power-up, set:
• set Reg 07h [11] = 1 to enable lock-detect counters
• set Reg 07h [14] = 1 to enable the lock-detect timer
• set Reg 07h [20] = 1 to train the lock-detect timer
These bits can all be written simultaneously.
On any change of the PD frequency (via either the external reference frequency, or the R divider setting (Reg 02h)),
the lock-detect circuit should be retrained by toggling Reg 07h [20] Off and then back On.
The lock-detect indication can be read from the SPI via Reg 12h[1], or can be exported on the LD_SDO pin via the
GPO mux(Reg 0Fh[4:0]). See LD_SDO pin description for more information.
Cycle Slip Prevention (CSP)
When changing frequency and the VCO is not yet locked to the reference, the instantaneous frequencies of the two PD
inputs are different, and the phase difference of the two inputs at the PD varies rapidly over a range much greater than
+/-2π radians. Since the gain of the PD varies linearly with phase up to +/-2π, the gain of a conventional PD will cycle
from high gain, when the phase difference approaches a multiple of 2π, to low gain, when the phase difference is
slightly larger than 0 radians. The output current from the charge pump will cycle from maximum to minimum even
though the VCO has not yet reached its final frequency.
The charge on the loop filter small cap may actually discharge slightly during the low gain portion of the cycle. This can
make the VCO frequency actually reverse temporarily during locking. This phenomenon is known as cycle slipping.
Cycle slipping causes the pull-in rate during the locking phase to vary cyclically. Cycle Slipping increases the time to
lock to a value much greater than that predicted by normal small signal Laplace analysis.
The HMC703LP4E mitigates the effects of cycle-slips by increasing the charge-pump current when the phase error is
larger than ~220 degrees or ~14 ns (whichever is less as measured by the lock-detect circuit). The circuit is normally
most effective for PD frequencies <= 50 MHz.
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