HMC703LP4E Datasheet, PDF (43/58 Pages) Hittite Microwave Corporation – 8 GHZ FRACTIONAL SYNTHESIZER

v02.0813
HMC703LP4E
8 GHz fractional synthesizer
cific address, it is necessary in the first SPI cycle to write the desired address to Reg 00h[4:0], then in the next SPI cycle
the desired data will be available on LD_SDO.
An example of the Open Mode two cycle procedure to read from any random address is as follows:
a. The Master (host), on the first 24 falling edges of SCK places 24 bit data, d23:d0, MSB first, on SDI
as shown in Figure 44. d23:d5 should be set to zero. d4:d0 = address of the register to be READ on
the next cycle.
b. the slave (synthesizer) shifts in data on SDI on the first 24 rising edges of SCK
c. Master places 5 bit register address , r4:r0, ( the address the WRITE ADDRESS register), MSB first,
on the next 5 falling edges of SCK (25-29). r4:r0=00000.
d. Slave shifts the register bits on the next 5 rising edges of SCK (25-29).
e. Master places 3 bit chip address, a2:a0, MSB first, on the next 3 falling edges of SCK (30-32).The
HMC703LP4E chip address is fixed at 000.
f. Slave shifts the chip address bits on the next 3 rising edges of SCK (30-32).
g. Master asserts SEN after the 32nd rising edge of SCK.
h. Slave registers the SDI data on the rising edge of SEN.
i. Master clears SEN to complete the address transfer of the two part READ cycle.
j. If we do not wish to write data to the chip at the same time as we do the second cycle , then it is
recommended to simply rewrite the same contents on SDI to Register zero on the READ back part
of the cycle.
k. Master places the same SDI data as the previous cycle on the next 32 falling edges of SCK.
l. Slave (synthesizer) shifts the SDI data on the next 32 rising edges of SCK.
m. Slave places the desired data (i.e. data from address in Reg 00h[4:0 ]) on LD_SDO on the next 32
rising edges of SCK. Lock Detect is disabled.
n. Master asserts SEN after the 32nd rising edge of SCK to complete the cycle and revert back to Lock
Detect on LD_SDO.
Note that if the chip address bits are unrecognized (a2:a0), the slave will tri-state the LD_SDO output to prevent a pos-
sible bus contention issue.
Table 12. SPI Open Mode - Read Timing Characteristics
Parameter
Conditions
Min.
t1
SDI setup time
3
t2
SDI hold time
3
t3
SEN low duration
10
t4
SEN high duration
10
t5
SCK Rising Edge to SDO time
t6
SEN to SCK Recovery Time
10
t7
SCK 32 Rising Edge to SEN Rising Edge
10
Typ.
Max.
8.2+0.2ns/pF
Units
ns
ns
ns
ns
ns
ns
ns
6 - 43
F^Irrliniecgo^fseohpr_ntrsomsp_enoasftir_isibtoi_hic^ngilrirtde_yafunpi,^rstnaed_airdstsihee_sbesuyl^dmti_hiv_mebae_dtypmlbr_iAcyay_anyAta9ioa_rlnoen7agsn_luoo8dlDrgt-^eofDr₂^vt_toheio_m5^ceveri_0cwisp_tesi-ssil_use3afsobeuc3_r.neie4_dtSliseep3^vuro_eescader_inf,d_iyc•^tnoae_optriabr_oftens_oe9srn:^a_7tascnH_ou8^cyrbui_j-ipernt2^aacft_rttti^e_5ient_tnoe_g0^atecnr_-mhdiM_g3aehnrn3tei_gstc^lsei₇^aor_{obwf3oflAiept}w_{hn.faoaatHuel}a_otoxngv^wntsoe_{Deotviecr•}^evC_eori,.ctheo_NnesOoor_r. prod^FOPre^ohna^r_roet_npiO_To_erei:nn^cc7e,-_h8,ln2_1inod-3leEe_o2lgil_9via_yz^e-_t4a^rWy7_wb^,a0ye^a_w0,nt_•Pwh^d.OO_.^tDh^or.d_irBeptitov_rli^axet_ocen9,^e_.l1iCc_n0oeo6rh^d,_mae^eNtl^rwom^s:rwws^Awofⁿo_o.aadr^lnd^o,agM,_loM_ADge.0A_cv2oic0m0^e61^s2,8_-9I2ⁿ¹4_0c.6,
Trademarks and registered trademarks are the property of their_Ares_pp_pec_lt_iiv_ce_aow_tin_oer_ns. _{Support: [e-mail] m}Support: Phone: 1-800-ANALOG-D