HMC703LP4E Datasheet, PDF (40/58 Pages) Hittite Microwave Corporation – 8 GHZ FRACTIONAL SYNTHESIZER

v02.0813
HMC703LP4E
8 GHz fractional synthesizer
Typical HMC Open Mode serial port operation can be run with SCK at speeds up to 50 MHz.
Serial Port HMC Mode Details
Typical serial port HMC Mode operation can be run with SCK at speeds up to 50MHz.
HMC Mode - Serial Port WRITE Operation
AVDD = DVDD = 3.3V +/-10%, AGND = DGND = 0V
Table 9. SPI HMC Mode - Write Timing Characteristics
Parameter
Conditions
Min.
Typ.
Max.
Units
t1
SEN to SCK setup time
t2
SDI to SCK setup time
t3
SCK to SDI hold time
t4
SEN low duration
t5
SCK to SEN fall
Max SPI Clock Frequency
8
3
3
20
10
50
nsec
nsec
nsec
nsec
nsec
MHz
A typical HMC Mode WRITE cycle is shown in Figure 41.
a. The Master (host) both asserts SEN (Serial Port Enable) and clears SDI to indicate a WRITE cycle,
followed by a rising edge of SCK.
b. The slave (synthesizer) reads SDI on the 1st rising edge of SCK after SEN. SDI low indi­cates a Write
cycle (/WR).
c. Host places the six address bits on the next six falling edges of SCK, MSB first.
d. Slave shifts the address bits in the next six rising edges of SCK (2-7).
e. Host places the 24 data bits on the next 24 falling edges of SCK, MSB first.
f. Slave shifts the data bits on the next 24 rising edges of SCK (8-31).
g. The data is registered into the chip on the 32nd rising edge of SCK.
h. SEN is cleared after a minimum delay of t₅. This completes the write cycle.
Figure 41. Serial Port Timing Diagram - HMC Mode WRITE
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