HMC703LP4E Datasheet, PDF (45/58 Pages) Hittite Microwave Corporation – 8 GHZ FRACTIONAL SYNTHESIZER

v02.0813
HMC703LP4E
8 GHz fractional synthesizer
REGISTER MAP
Table 13. Reg 00h ID Register (Read Only)
BIT
TYPE
NAME
W DEFLT
[23:0]
RO
chip_ID
24 97370h
PLL ID
DESCRIPTION
Table 13. Reg 00h Open Mode Read Address/RST Strobe Register (Write Only) (Continued)
BIT
TYPE
NAME
W DEFLT
DESCRIPTION
[4:0]
WO
ReadAddr
5
0
Write the intended read address to this register for Open Mode
register reads. On the 1st SPI clock of the next cycle the data is
read and the shift-out begins.
Table 13. Reg 00h Open Mode Read Address Register (Write Only) (Continued)
BIT
TYPE
NAME
W DEFLT
DESCRIPTION
5
WO
SoftRst
10
Soft-reset. When 1, it Resets the registers to POR state, and is-
sues POR to analog.
Table 14. Reg 01h RST Register
BIT
TYPE
0
R/W
NAME
EnPinSel
1
R/W
[9:2]
R/W
EnFromSPI
EnKeepOns
10
R/W
EnSyncChpDis
W DEFLT
DESCRIPTION
0
0
If 1, the master chip enable is taken from the pin rather than from
the SPI.
1
1
The master Enable from the SPI. Write a 0 to power-down the chip.
8
0
While the chip is disabled, the user has the option to keep the
following sub-circuits active by writing a 1 to the appropriate bits.
[2] Bias, [3] PFD, [4] CHP, [5] RefBuf, [6] VCOBuf, [7] GPO, [8]
VCODIVA, [9] VCODIVB
1
0
If 1, then following a disable event, the charge-pump is disabled
synchronously on the falling edge of the divided reference to tri-
state the charge pump without transient.
Table 15. Reg 02h REFDIV Register
BIT
TYPE
NAME
W
[13:0]
R/W
rdiv
14
DEFLT
1
DESCRIPTION
Reference Divider ’R’ Value
Divider use also requires refBufEn Reg08[3]=1
min 1d
max 16383d
6 - 45
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