Z8018010VSG Datasheet, PDF (76/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
70
CYC1, 0: Cycle Interval (bit 1,0)—CYC1 and CYC0 specify the interval (in clock
cycles) between refresh cycles. In the case of dynamic RAMs requiring 128 refresh cycles
every 2 ms (or 256 cycles in every 4 ms), the required refresh interval is less than or equal to
15.625 µs. The underlined values indicate the best refresh interval depending on CPU clock
frequency. CYC0 and CYC1 are cleared to 0 during RESET (see Table 19).
Table 19. DRAM Refresh Intervals
Time Interval
CYC1 CYC0 Insertion Interval Ø: 10 MHz 8 MHz 6 MHz 4 MHz 2.5 MHz
0
0
10 states
(1.0 µs)* (1.25 µs)* 1.66 µs 2.5 µs 4.0 µs
0
1
20 states
(2.0 µs)* (2.5 µs)* 3.3 µs 5.0 µs 8.0 µs
1
0
40 states
(4.0 µs)* (5.0 µs)* 6.6 µs 10.0 µs 16.0 µs
1
1
80 states
(8.0 µs)* (10.0 µs)* 13.3 µs 20.0 µs 32.0 µs
*Calculated interval.
Refresh Control and RESET
After RESET, based on the initialized value of RCR, refresh cycles occur with an interval of
10 clock cycles and be 3 clock cycles in duration.
Dynamic RAM Refresh Operation
1. REFRESH CYCLE insertion is stopped when the CPU is in the following states:
a. During RESET
b. When the bus is released in response to BUSREQ
c. During SLEEP mode
d. During WAIT states
2. Refresh cycles are suppressed when the bus is released in response to BUSREQ.
However, the refresh timer continues to operate. The time at which the first refresh cycle
occurs after the Z80180 reacquires the bus depends on the refresh timer, and possesses
no timing relationship with the bus exchange.
3. Refresh cycles are suppressed during SLEEP mode. If a refresh cycle is requested during
SLEEP mode, the refresh cycle request is internally latched (until replaced with the next
refresh request). The latched refresh cycle is inserted at the end of the first machine
cycle after SLEEP mode is exited. After this initial cycle, the time at which the next
refresh cycle occurs depends on the refresh time and carries no relationship with the exit
from SLEEP mode.
PS014004-1106
Architecture