Z8018010VSG Datasheet, PDF (32/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
26
Table 8. Z80180-8 AC Characteristics (continued)
No Symbol Item
32 t_INTS INT Hold Time from Ø Fall
33 t_NMIW NMI Pulse Width
34 t_BRS BUSREQ Set-up Time to Ø Fall
35 t_BRH BUSREQ Hold Time from Ø Fall
36 t_BAD1 Ø Rise to BUSACK Fall Delay
37 t_BAD2 Ø Fall to BUSACK Rise Delay
38 t_BZD Ø Rise to Bus Floating Delay Time
39 t_MEWH MREQ Pulse Width (High)
40 t_MEWL MREQ Pulse Width (Low)
41 t_RFD1 Ø Rise to RFSH Fall Delay
42 t_RFD2 Ø Rise to RFSH Rise Delay
43 t_HAD1 Ø Rise to HALT Fall Delay
44 t_HAD2 Ø Rise to HALT Rise Delay
45 t_DRQS /DREQi Set-up Time to Ø Rise
46 t_DRQH /DREQi Hold Time from Ø Rise
47 t_TED1 Ø Fall to TENDi Fall Delay
48 t_TED2 Ø Fall to TENDi Rise Delay
49 t_ED1 Ø Rise to E Rise Delay
50 t_ED2 Ø Fall or Rise to E Fall Delay
51 P_WEH E Pulse Width (High)
52 P_WEL E Pulse Width (Low)
53 t_Er
Enable Rise Time
54 t_Ef
Enable Fall Time
55 t_TOD Ø Fall to Timer Output Delay
56 t_STDI CSIO Transmit Data Delay Time (Internal Clock
Operation)
57 t_STDE CSIO Transmit Data Delay Time (External Clock
Operation)
Z80180-8
Min Max Unit
40 –
ns
100 –
ns
40 –
ns
40
ns
–
70 ns
–
70 ns
–
90 ns
90 –
ns
100 –
ns
–
80 ns
–
80 ns
–
80 ns
–
80 ns
40 –
ns
40 –
ns
–
60 ns
–
60 ns
–
70 ns
–
70 ns
65 –
ns
130 –
ns
–
20 ns
–
20 ns
–
200 ns
–
200 ns
–
7.5tcy ns
c
+200
PS014004-1106
Architecture