Z8018010VSG Datasheet, PDF (57/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
51
ASCI Extension Control Registers, Channel 0 and 1
ASCI Extension Control Register 0(ASEXT0 I/O Address = 12h)
Bit 7
6
5
4
3
2
1
0
Reserved
DCDO CTSO
BRGO Break
Send
XI _{Mode Nab}
Break Break
ASCI Extension Control Register 1 (ASEXT1 I/O Address = 13h)
Bit
7
6
5
4
3
2
1
0
Reserved Reserved Reserved ^XI
BRGI
Mode
Break
Enab
Break
Send
Break
Figure 42. ASCI Extension Control Registers, Channel 0 and 1
DCD0 dis (bit 6, ASCI0 only)—If bit 0 of the Interrupt Edge Register is 0 to select the
DCD0 function for the DCD0/CKA1 pin, and this bit is 0, the DCD0 pin auto-enables the
ASCI0 receiver. When the pin is negated/High, the Receiver is held in a RESET state. If bit 0
of the IER is 0 and this bit is 1, the state of the DCD-pin has no effect on receiver operation.
In either state of this bit, software can read the state of the DCD0 pin in the STAT0 register,
and the receiver interrupts on a rising edge of DCD0.
CTS0 dis (bit 5, ASCI0 only)—If bit 5 of the System Configuration Register is 0 to
select the CTS0 function of the CTS0/RXS pin, and this bit is 0, then the CTS0 pin auto-
enables the ASCIO transmitter, in that when the pin is negated (High), the TDRE bit in the
STAT0 register is forced to 0. If bit 5 of the System Configuration Register is 0 and this bit is
1, the state of the CTS0 pin exhibits no effect on the transmitter. Regardless of the state of
this bit, software can read the state of the CTS0 pin the CNTLB0 register.
X1 (bit 4)—If this bit is 1, the clock from the Baud Rate Generator or CKA pin is received
as a 1X bit clock (sometimes called isochronous mode). In this mode, receive data on the
RXA pin must be synchronized to the clock on the CKA pin, regardless of whether CKA is an
input or an output. If this bit is 0, the clock from the Baud Rate Generator or CKA pin is
divided by 16 or 64 per the DR bit in CNTLB register, to obtain the actual bit rate. In this
mode, receive data on the RXA pin is not required to be synchronized to a clock.
BRG Mode (bit 3)—If the SS2–0 bits in the CNTLB register are not 111, and this bit is 0,
the ASCI Baud Rate Generator divides PHI by 10 or 30, depending on the DR bit in CNTLB,
and then by a power of two selected by the SS2–0 bits, to obtain the clock that is presented to
the transmitter and receiver and that can be output on the CKA pin. If SS2–0 are not 111, and
this bit is 1, the Baud Rate Generator divides PHI by twice (the 16-bit value programmed
into the Time Constant Registers, plus 2). This mode is identical to the operation of the baud
rate generator in the ESCC.
Break Enable (bit 2)—If this bit is 1, the receiver detects break conditions and report
them in bit 1, and the transmitter sends breaks under the control of bit 0.
PS014004-1106
Architecture