Z8018010VSG Datasheet, PDF (41/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
35
E Clock Timing (Memory READ/WRITE Cycle, I/O READ/WRITE Cycle)
T₁
T₂
T_W
ø
E
(Memory READ/WRITE)
49
49
E
(I/O READ)
49
E
(I/O WRITE)
T_W
T₃
50
50
50
15
16
D₀–D₇
Figure 20. E Clock Timing (Memory R/W Cycle, I/O R/W Cycle)
E
PH1ø
E
49
50
BUS RELEASE mode
SLEEP mode
SYSTEM STOP mode
Figure 21. E Clock Timing (Bus Release, Sleep, System Stop Modes
E Clock Timing (Bus Release, Sleep, System Stop Modes)
E Clock Timing (Minimum timing example of
T₂
T_W
T₃
T₁
T₂
E
Example
I/O READ
→ Opcode Fetch
50 ₅₂
49
50
49
54
53
51
53
54
Figure 22. E Clock Timing (P_WEL and P_WEH Minimum Timing)
PS014004-1106
Architecture