Z8018010VSG Datasheet, PDF (25/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
19
SLEEP Mode—Enter SLEEP mode by keeping the IOSTOP bit (ICR5) bits 3 and 6 of the
CPU Control Register (CCR3, CCR6) all zero and executing the SLEEP instruction. The
oscillator and PHI output continue operating, but are blocked from the CPU core and DMA
channels to reduce power consumption. DRAM refresh stops but interrupts and
granting to external master can occur. Except when the bus is granted to an external master,
A19–0 and all control signals except HALT are maintained High. HALT is Low. I/O opera-
tions continue as before the SLEEP instruction, except for the DMA channels.
The Z80180 leaves SLEEP mode in response to a Low on RESET, an
interrupt request from an on-chip source, an external request on NMI, or an external request
on INT0, INT1, or INT2.
If an interrupt source is individually disabled, it cannot bring the Z80180 out of SLEEP
mode. If an interrupt source is individually enabled, and the IEF bit is 1 so that interrupts are
globally enabled (by an EI instruction), the highest priority active interrupt occurs, with the
return address being the instruction after the SLEEP instruction. If an interrupt source is indi-
vidually enabled, but the IEF bit is 0 so that interrupts are globally disabled (by a DI instruc-
tion), the Z80180 leaves SLEEP mode by simply executing the following instruction(s).
This provides a technique for synchronization with high- speed external events without
incurring the latency imposed by an interrupt response sequence. Figure 14 displays the
timing for exiting SLEEP mode due to an interrupt request.
Note: The Z80180 takes about 1.5 clocks to restart.
SLEEP 2nd Opcode
Fetch Cycle
T₂
T₃
T₁
φ
SLEEP Mode
T₂
T_S
T_S
Opcode Fetch or Interrupt
Acknowledge Cycle
T₁
T₂
T₃
INT_i, NMI
A₀–A₁₉
HALT
SLEEP 2nd Opcode Address
FFFFFh
M1
Figure 14. SLEEP Timing
IOSTOP Mode—IOSTOP mode is entered by setting the IOSTOP bit of the I/O Control
Register (ICR) to 1. In this case, on-chip I/O (ASCI, CSIO, PRT) stops operating. However,
the CPU continues to operate. Recovery from IOSTOP mode is by resetting the IOSTOP bit
in ICR to 0.
SYSTEM STOP Mode—SYSTEM STOP mode is the combination of SLEEP and IOSTOP
modes. SYSTEM STOP mode is entered by setting the IOSTOP bit in ICR to 1 followed by
PS014004-1106
Architecture