Z8018010VSG Datasheet, PDF (54/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
CSIO Transmit/Receive Data Register
(TRDR: I/O Address = 0Bh)
ASCI Receive Register Channel 1R
76 54 32 1
—— —— — — —
CSIO Transmit/Receive Data
Figure 36. CSI/O Receive Register Channel 1R
Timer Data Register Channel 0L
TMDR0L: OCH
ASCI Receive Register Channel 1R
0Ch
76
——
54 32 1
—— — — —
Timer Data
Figure 37. Timer Data Register Channel Low
Timer Data Register Channel 0H
TMDR0H: ODH
Timer Data Register Channel High
0Dh
76 54 32 1
—— —— — — —
PS014004-1106
Timer Data
Figure 38. Timer Data Register Channel High
48
Architecture