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| Z8018010VSG Datasheet, PDF (24/85 Pages) Zilog, Inc. – Microprocessor Unit | |||
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Z80180
Microprocessor Unit
18
HALT and Low-Power Operating ModesâThe Z80180 can operate in five modes with
respect to activity and power consumption:
⢠Normal Operation
⢠HALT mode
⢠IOSTOP mode
⢠SLEEP mode
⢠SYSTEM STOP mode
Normal OperationâThe Z80180 processor is fetching and running a program. All enabled
functions and portions of the device are active, and the HALT pin is High.
HALT ModeâThis mode is entered by the HALT instruction. Thereafter, the Z80180
processor continually fetches the following opcode but does not execute it, and drives the
HALT, ST and M1 pins all Low. The oscillator and PHI pin remain active, interrupts and bus
granting to external masters, and DRAM refresh can occur and all on-chip I/O devices
continue to operate including the DMA channels.
The Z80180 leaves HALT mode in response to a Low on RESET, on to an interrupt from an
enabled on-chip source, an external request on NMI, or an enabled external request on INT0,
INT1, or INT2. In case of an interrupt, the return address is the instruction following the
HALT instruction; at that point the program can either branch back to the HALT instruction
to wait for another interrupt, or can examine the new state of the system/application and
respond appropriately.
HALT Opcode Fetch Cycle
T2
T3
T1
Ï
HALT Mode
T2
T3
Interrupt
Acknowledge Cycle
T1
T2
INTi, NMI
A0âA19 HALT Opcode Address
HALT
HALT Opcode Address + 1
M1
MREQ
RD
Figure 13. HALT Timing
PS014004-1106
Architecture
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