Z8018010VSG Datasheet, PDF (42/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
36
Timer Output Timing
Timer Data
Reg.=0000h
A₁₈/T_OUT
55
Figure 23. Timer Output Timing
Execution Cycle
SLEEP Instruction fetch
Next Opcode fetch
T₃
T₁
T₂
T_S
T_S
T₁
T₂
ø
INTi
NMI
A₀–A₁₈
MREQ, M1
RD
HALT
31
32
33
43
44
Figure 24. SLEEP Execution Cycle
PS014004-1106
Architecture