Z8018010VSG Datasheet, PDF (71/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
65
MMOD: Memory Mode Channel 0 (bit 1). When channel 0 is configured for memory
to/from memory transfers there is no REQUEST HANDSHAKE signal to control the transfer
timing. Instead, two automatic transfer timing modes are selectable: burst (MMOD = 1) and
cycle steal (MMOD = 0). For burst memory to/from memory transfers, the DMAC takes
control of the bus continuously until the DMA transfer completes (the byte count register is
0). In CYCLE STEAL mode, the CPU is provided a cycle for each DMA byte transfer cycle
until the transfer is completed.
For channel 0 DMA with I/O source or destination, the selected REQUEST HANDSHAKE
signal times the transfer and MMOD is ignored. MMOD is cleared to 0 during RESET.
DMA/WAIT Control Register (DCNTL)
DCNTL controls the insertion of wait states into DMAC (and CPU) accesses of memory or
I/O. DCNTL also defines the Request signal for each channel as level or edge sense. DCNTL
also sets the DMA transfer mode for channel 1, which is limited to memory to/from I/O
transfers.
DMA/WAIT Control Register (DCNTL: I/O Address = 32h)
Bit 7
6
5
4
3
2
1
0
MWI1 MWI0 IWI1
R/W R/W R/W
IWI0 DMS1 DMS0 DIM1 DIM0
R/W R/W R/W R/W R/W
Figure 67. DMA/WAIT Control Register (DCNTL: I/O Address = 32h
MWI1, MWI0: Memory Wait Insertion (bits 7-6)—Specifies the number of wait states
introduced into CPU or DMAC memory access cycles. MWI1 and MWI0 are set to 1 during
RESET.
IWI1, IWI0: I/O Wait Insertion (bits 5-4)—Specifies the number of wait states
introduced into CPU or DMAC I/O access cycles. IWI1 and IWI0 are set to 1 during RESET.
DMS1, DMS0: DMA Request Sense (bits 3-2)—DMS1 and DMS0 specify the DMA
request sense for channel 0 and channel 1 respectively. When reset to 0, the input is level
sense. When set to 1, the input is edge sense. DMS1 and DMS0 are cleared to 0 during
RESET.
Typically, for an input/source device, the associated DMS bit must be
programmed as 0 for level sense because the device undertakes a relatively long period to
update its REQUEST signal after the DMA channel reads data from it in the first of the two
machine cycles involved in transferring a byte.
An output/destination device takes much less time to update its REQUEST signal, after the
DMA channel starts a WRITE operation to it, as the
PS014004-1106
Architecture