Z8018010VSG Datasheet, PDF (52/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
46
FE: Framing Error (bit 4)—A framing error is detected when the stop bit of a character is
sampled as 0/SPACE. However, this status bit is not set until or unless the error character
becomes the oldest one in the RxFIFO. FE is cleared when software writes a 1 to the EFR bit
in the CNTLA register, and also by RESET, in IOSTOP mode, and for ASCIO if the DCDO
pin is auto-enabled and is negated (High).
REI: Receive Interrupt Enable (bit 3)—RIE must be set to 1 to enable ASCI receive
interrupt requests. When RIE is 1, the receiver requests an interrupt when a character is
received and RDRF is set, but only if neither DMA channel sets its request-routing field to
receive data from this ASCI. That is, if SM1–0 are 11 and SAR17–16 are 10, or DIM1 is 1 and
IAR17–16 are 10, then ASCI1 does not request an interrupt for RDRF. If RIE is 1, either ASCI
requests an interrupt when OVRN, PE or FE is set, and ASCI0 requests an interrupt when
DCD0 goes High. RIE is cleared to 0 by RESET.
DCD0: Data Carrier Detect (bit 2 STAT0)—If bit 0 of the Interrupt Edge Register
(IER0) is 0, the DCD0/CKA1 pin features the DCD0 function, and this bit is set to 1 when the
pin is High. It is cleared to 0 on the first READ of STAT0 following the pin's transition from
High to Low and during RESET. When IER0 is 0, bit 6 of the ASEXT0 register is 0 to select
auto-enabling, and the pin is negated (High), the bit 2 of STAT1 is not used.
TDRE: Transmit Data Register Empty (bit 1)—TDRE = 1 indicates that the TDR is
empty and the next transmit data byte is written to TDR. After the byte is written to TDR,
TDRE is cleared to 0 until the ASCI transfers the byte from TDR to the TSR and then TDRE is
again set to 1. TDRE is set to 1 in IOSTOP mode and during RESET. On ASCIO, if the CTS0
pin is auto-enabled in the ASEXT0 registers and the pin is High, TDRE is reset to 0.
TIE: Transmit Interrupt Enable (bit 0)—TIE must be set to 1 to enable ASCI transmit
interrupt requests. If TIE = 1, an interrupt is requested when TDRE = 1. TIE is cleared to 0
during RESET.
CSIO Control/Status Register
CSIO Control
CNTR: I/O Address = 0Ah—CNTR is used to monitor CSIO status, enable and disable the
CSIO, enable and disable interrupt generation, and select the data clock speed and source.
Bit
7
6
5
4
3
2
1
0
EF
EIE
RE
TE
__
SS2
SS1
SS0
R
R/W
R/W
R/W
R/W
R/W
R/W
Figure 35. CSIO Control Register
EF: End Flag (bit 7)—EF is set to 1 by the CSIO to indicate completion of an 8-bit data
transmit or receive operation. If the End Interrupt Enable (EIE) bit = 1 when EF is set to 1, a
CPU interrupt request is generated. Program access of TRDR only occurs if EF = 1. The CSIO
PS014004-1106
Architecture