Z8018010VSG Datasheet, PDF (31/85 Pages) Zilog, Inc. – Microprocessor Unit

Table 8. Z80180-8 AC Characteristics (continued)
No Symbol Item
8 t_MED1 Ø Fall to MREQ Fall Delay
9 t_RDD1 Ø Fall to RD Fall Delay IOC = 1
Ø Rise to RD Rise Delay IOC = 0
10 t_M1D1 Ø Rise to M1 Fall Delay
11 t_AH
Address Hold Time from
(MREQ, IOREQ, RD, WR)
12 t_MED2
13 t_RDD2
14 t_M1D2
15 t_DRS
16 t_DRH
17 t_STD1
18 t_STD2
19 t_WS
20 t_WH
21 t_WDZ
22 t_WRD1
23 t_WDD
24 t_WDS
25 t_WRD2
26 t_WRP
26a
Ø Fall to MREQ Rise Delay
Ø Fall to RD Rise Delay
Ø Rise to M1 Rise Delay
Data Read Set-up Time
Data Read Hold Time
Ø Fall to ST Fall Delay
Ø Fall to ST Rise Delay
WAIT Set-up Time to Ø Fall
WAIT Hold Time from Ø Fall
Ø Rise to Data Float Delay
Ø Rise to WR Fall Delay
Ø Fall to WRITE Data Delay Time
WRITE Data Set-up Time to WR Fall
Ø Fall to WR Rise Delay
WR Pulse Width
WR Pulse Width (I/O WRITE Cycle)
27 t_WDH
28 t_IOD1
WRITE Data Hold Time from (WR Rise)
Ø Fall to IORQ Fall Delay IOC = 1
Ø Rise to IORQ Fall Delay IOC = 1
29 t_IOD2
30 t_IOD3
31 t_INTS
Ø Fall to IORQ Rise Delay
M1 Fall to IORQ Fall Delay
INT Set-up Time to Ø Fall
PS014004-1106
Z80180
Microprocessor Unit
25
Z80180-8
Min Max Unit
–
50 ns
–
50 ns
–
60
–
70 ns
20 –
ns
–
50 ns
–
50 ns
–
70* ns
30 –
ns
0
–
ns
–
70 ns
–
70 ns
40 –
ns
40 –
ns
–
70 ns
–
60 ns
–
80 ns
20 –
ns
–
60 ns
130 –
ns
255 –
ns
15 –
–
50 ns
–
60
–
50 ns
250 –
ns
40 –
ns
Architecture