Z8018010VSG Datasheet, PDF (63/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
57
In the R1 and Z Mask, these DMA registers are expanded from 4 bits to 3 bits in the
Note: _{package version of CP-68.}
Table 15. DMA Transfer Requests
A19* A18 A17 A16 DMA Transfer Request
X
X
0
0
DREQ0
X
X
0
1
TDR0 (ASCI0)
X
X
1
0
TDR1 (ASCI1)
X
X
1
1
Not Used
DMA Byte Count Register Channel 0
(BCRO: I/O ADDRESS = 26h to 27h) specifies the number of bytes to be transferred. This reg-
ister contains 16 bits and may specify up to 64 KB transfers. When one byte is transferred,
the register is decremented by 1. If n bytes are transferred, n must be stored before the DMA
operation.
Note: All DMA Count Register channels are undefined during RESET.
DMA Byte Count Register Channel 0L
Mnemonic BCR0L: Address 26h
DMA Byte Count Register
76 54 32 1 0
Counting Data
Figure 54. DMA Byte Count Register 0L
PS014004-1106
Architecture