Z8018010VSG Datasheet, PDF (72/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
66
second machine cycle of the two cycles involved in transferring a byte. With zero-wait state
I/O cycles, which apply only to the ASCIs, it is impossible for a device to update its
REQUEST signal in time, and edge sensing must be used.
With one-wait-state I/O cycles (the fastest possible except for the ASCIs), it is unlikely that
an output device is able to update its REQUEST in time, and edge sense is required for output
to the ESCC and bidirectional Centronics controller, and is recommended for external output
devices connected to T_OUT/DREQ.
With two or more wait states in I/O cycles, external output devices on T_OUT/DREQ can use
edge or level sense depending on their characteristics; edge sense is still recommended for
output on the ESCC and bidirectional Centronics controller.
DIM1, DIM0: DMA Channel 1 I/O and Memory Mode (bits 1-0)—Specifies the
source/destination and address modifier for channel 1 memory to/from I/O transfer modes.
DIM1 and DIM0 are cleared to 0 during RESET.
Interrupt Vector Low Register
Table 18. Channel 1 Transfer Mode
DIM1 DMI0 Transfer Mode Address Increment/Decrement
0
0
Memory→I/O MAR1 +1, IAR1 fixed
0
1
Memory→I/O MAR1–1, IAR1 fixed
1
0
I/O→Memory IAR1 fixed, MAR1 + 1
1
1
I/O→Memory IAR1 fixed, MAR1 –1
Mnemonic: IL
Address 33
Bits 7–5 of IL are used as bits 7–5 of the synthesized interrupt vector during interrupts for the
INT1 and INT2 pins and for the DMAs, ASCIs, PRTs, and CSIO. These three bits are cleared
to 0 during RESET (Figure 68).
Interrupt Vector Low Register (IL: I/O Address = 33h)
Bit ⁷
6
5
4
3
IL 7 IL 6 IL 5 _––
––
R/W R/W R/W
2
1
0
––
––
––
Programmable
Interrupt Source Dependent Code
Figure 68. Interrupt Vector Low Register (IL: I/O Address = 33h)
PS014004-1106
Architecture