Z8018010VSG Datasheet, PDF (70/85 Pages) Zilog, Inc. – Microprocessor Unit

Z80180
Microprocessor Unit
64
Mnemonic DMODE
Address 31h
DMA Mode Register (DMODE: I/O Address = 31h)
Bit 7
6
5
4
3
2
1
0
DM1 DM0 SM1 SM0 MMOD
R/W R/W R/W R/W R/W
Figure 66. DMA Mode Register (DMODE: I/O Address = 31h)
DM1, DM0: Destination Mode Channel 0 (bits 5,4)—Specifies whether the
destination for channel 0 transfers is memory or I/O, and whether the address must be incre-
mented or decremented for each byte transferred. DM1 and DM0 are cleared to 0 during
RESET (see Table 16).
Table 16. Channel 0 Destination
DM1
0
0
1
1
DM0
0
1
0
1
Memory I/O
Memory
Memory
Memory
I/O
Memory Increment/Decrement
+1
–1
fixed
fixed
SM1, SM0: Source Mode Channel 0 (bits 3, 2)—Specifies whether the source for
channel 0 transfers is memory or I/O, and whether the address must be incremented or
decremented for each byte transferred (see Table 17).
Table 17. Channel 0 Source
SM1
0
0
1
1
SM0
0
1
0
1
Memory I/O
Memory
Memory
Memory
I/O
Memory Increment/Decrement
+1
–1
fixed
fixed
Table 18 lists all DMA transfer mode combinations of DM0, DM1, SM0, and SM1. Because
I/O to/from I/O transfers are not implemented, 12 combinations are available.
PS014004-1106
Architecture